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ORCIDYoung-Jun Park 0002
Person information
- affiliation: Ryerson University, Department of Electrical and Computer Engineering, Toronto, ON, Canada
- affiliation: TSMC Design Technology Canada Inc., Kanata, ON, Canada
Other persons with the same name
- Young-Jun Park (aka: Young Jun Park) — disambiguation page
- Young-Jun Park 0001
![[0000-0003-0018-2310]](https://devdomain4test.ir/img/orcid-mark.12x12.png "0000-0003-0018-2310")
— Seoul National University, Department of Biosystems Engineering, Convergence Major in Global Smart Farm, Korea - Young-Jun Park 0003 — Kyungpook National University, Intelligent Construction Automation Center, Korea
- Young-Jun Park 0004 — Korea Military Academy, Department of Civil Engineering and Environmental Sciences, Seoul, Korea
- Young-Jun Park 0005 (aka: Young Jun Park 0005) — Sungkyunkwan University, College of Information and Communication Engineering, Suwon, Korea
- Young-Jun Park 0006 (aka: Young Jun Park 0006) — SK hynix Semiconductor, Icheon, Korea
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2010 – 2019
- 2018
[j2]Young Jun Park, Parth Parekh, Fei Yuan:
All-digital ΔΣ time-to-digital converter with Bi-Directional gated delay line time integrator. Microelectron. J. 81: 179-191 (2018)- 2017
- [j1]Young Jun Park, Fei Yuan:
Two-step pulse-shrinking time-to-digital converter. Microelectron. J. 60: 45-54 (2017) - [c7]Young Jun Park, Fei Yuan:
Low-power all-digital ΔΣ TDC with bi-directional gated delay line time integrator. MWSCAS 2017: 679-682 - [c6]Young Jun Park, Fei Yuan:
1-1 MASH ΔΣ time-to-digital converter with differential cascode time integrator. MWSCAS 2017: 1005-1008 - [c5]Young Jun Park, Fei Yuan:
All-digital ΔΣ TDC with differential bi-directional gated-delay-line time integrator. MWSCAS 2017: 1513-1516 - 2016
- [c4]Young Jun Park, Durand Jarrett-Amor, Fei Yuan:
Time integrator for mixed-mode signal processing. ISCAS 2016: 826-829 - [c3]Durand Jarrett-Amor, Young Jun Park, Fei Yuan:
Time-mode techniques for fast-locking phase-locked loops. ISCAS 2016: 1790-1793 - 2015
- [c2]Young Jun Park, Fei Yuan:
0.25-4 ns 185 MS/s 4-bit pulse-shrinking time-to-digital converter in 130 nm CMOS using a 2-step conversion scheme. MWSCAS 2015: 1-4 - [c1]Young Jun Park, Fei Yuan:
A 12.88 MS/s 0.28 pJ/conv.step 8-bit stage-interleaved pulse-shrinking time-to-digital converter in 130 nm CMOS. MWSCAS 2015: 1-4
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