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Jin Jin 0005
Person information
- affiliation: Nanjing University of Science and Technology (NJUST), Ministry of Education Key Laboratory of Near-Range RF Sensing ICs and Microsystems, China
- affiliation (PhD 2022): National ASIC System Engineering Research Center, Southeast University, Nanjing, China
- affiliation (2019-2021): University of Pavia, MicroLab, Italy
Other persons with the same name
- Jin Jin — disambiguation page
- Jin Jin 0001 — University of Toronto, Department of Electrical and Computer Engineering, Canada
- Jin Jin 0002
— Zhengzhou University, School of Information and Engineering, China (and 1 more) - Jin Jin 0003
— University of Queensland, School of Information Technology and Electrical Engineering, Brisbane, QLD, Australia - Jin Jin 0004
— Chinese Academy of Sciences, Institute of Computer Application, Chengdu, China
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2020 – today
- 2026
[j4]Bowei Xiao
, Jin Jin
, Haipeng Bai
, Wen Wu
, Danilo Manstretta
, Tongde Huang
:
A +43.3-dBm IIP3, Low-Power Transimpedance Amplifier Employing a Switched-Capacitor Amplifier-Based Transition-Band Pole-Zero Doublets Compensation Technique. IEEE J. Solid State Circuits 61(6): 2834-2845 (2026)
[c6]Junnan Guan, Hanzhang Cao, Jin Jin, Wen Wu, Tongde Huang:
A 14.0-to-17.3GHz Inter-Core 1st&2nd Harmonics Co-Circulation Quad-Core Inverse Class-F Oscillator Achieving 199.1dBc/Hz Peak FoM in 65nm CMOS. CICC 2026: 1-4
[c5]Jin Jin, Zhepu Xu, Bowei Xiao, Guisheng Yan, Danilo Manstretta, Wen Wu, Tongde Huang:
An Ultra-Low-Power Capacitive Stacking Receiver Front-End with a PVT-Robust Switched-Capacitor-Based Feed-Forward IM3 Cancellation Technique. CICC 2026: 1-4- 2025
[j3]Hanzhang Cao
, Sichen Gao
, Tongde Huang
, Xiaolong Liu
, Hao Wang
, Jin Jin
, Wen Wu
:
A Trifilar Transformer-Based Class-F23 VCO With Noise-Circulating Technology. IEEE Trans. Very Large Scale Integr. Syst. 33(8): 2118-2131 (2025)
[c4]Hanzhang Cao, Sichen Gao, Jin Jin
, Xiaolong Liu, Wen Wu, Tongde Huang:
34.5 An 18.5-to-23.6GHz Quad-Core Class-F23 Oscillator Without 2nd/3rd Harmonic Tuning Achieving 193dBc/Hz Peak FoM and 140-to-250kHz 1/f3PN Corner in 65nm CMOS. ISSCC 2025: 1-3- 2023
[c3]Hanzhang Cao
, Tongde Huang, Xiaolong Liu, Hao Wang, Jin Jin
, Wen Wu:
A 5.2GHz Trifilar Transformer-Based Class-F23 Noise Circulating VCO with FoM of 192.6 dBc/Hz. A-SSCC 2023: 1-3- 2022
[j2]Jin Jin
, Jianhui Wu
, Rinaldo Castello
, Danilo Manstretta
:
A 400-μW IoT Low-IF Voltage-Mode Receiver Front-End With Charge-Sharing Complex Filter. IEEE J. Solid State Circuits 57(7): 1957-1967 (2022)
[c2]Jin Jin, Simone Lecchi, Rinaldo Castello, Danilo Manstretta:
An FDD Auxiliary Receiver with a Highly Linear Low Noise Amplifier. ESSCIRC 2022: 309-312- 2021
[c1]Jin Jin, Jianhui Wu, Rinaldo Castello, Danilo Manstretta:
A 400-µW Low-IF IoT Receiver Front-End with Tunable Charge-Sharing Complex Filter. ESSCIRC 2021: 419-422- 2020
[j1]Chenggang Yan
, Jianhui Wu
, Jie Sun, Jin Jin
, Chen Hu:
A Low Phase Noise Open Loop Fractional-N Frequency Synthesizer With Injection Locking Digital Phase Modulator. IEEE Trans. Circuits Syst. II Express Briefs 67-II(3): 455-459 (2020)
Coauthor Index

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last updated on 2026-07-08 01:40 CEST by the dblp team
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