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ORCIDHyunwoo Lee 0013
Person information
- affiliation: Korea University, Department of Electronics and Electrical Engineering, Seoul, Korea
- affiliation: SK Hynix semiconductor Inc., Hyundai Electronics, Icheon, Korea
Other persons with the same name
- Hyunwoo Lee (aka: HyunWoo Lee, Hyun-Woo Lee, Hyun-woo Lee, Hyun Woo Lee) — disambiguation page
- Hyunwoo Lee 0001
![[0000-0001-7490-9936]](https://devdomain4test.ir/img/orcid-mark.12x12.png "0000-0001-7490-9936")
— Korea Institute of Energy Technology, Energy AI, Korea (and 2 more) - Hyunwoo Lee 0002 — Seoul National University, Department of Electrical and Computer Engineering, Seoul, South Korea (and 1 more)
- Hyunwoo Lee 0003 — Sangmyung University, Department of Emotion Engineering, Seoul, Korea
- Hyunwoo Lee 0004 — Yonsei University, Department of Biomedical Engineering, Wonju, Korea
- Hyunwoo Lee 0005 — Virginia Tech, Grado Department of Industrial and Systems Engineering, Blacksburg, VA, USA (and 1 more)
- Hyunwoo Lee 0006 — Yonsei University, School of Electrical and Electronic Engineering, Information and Telecommunication Lab, Seoul, Korea
- Hyunwoo Lee 0007 — Simon Fraser University, School of Engineering Science, Canada (and 1 more)
- Hyunwoo Lee 0008 (aka: Hyun-Woo Lee 0008) — Korea Institute of Science and Technology Information (KISTI), Science and Technology Security Research Center, Daejeon, Korea (and 1 more)
- Hyunwoo Lee 0009 — Korea Advanced Institute of Science and Technology (KAIST), Department of Mathematical Sciences, Daejeon, Korea (and 1 more)
- Hyunwoo Lee 0010 (aka: Hyun-Woo Lee 0010) — Texas A&M University, Department of Kinesiology & Sport Management, TX, USA
- Hyunwoo Lee 0011 (aka: Hyun-Woo Lee 0011) — Kyungpook National University, Smart Agriculture Innovation Centre, Department of Agricultural Civil Engineering, College of Agricultural and Life Sciences, Korea
- Hyunwoo Lee 0012 (aka: HyunWoo Lee 0012, Hyun-Woo Lee 0012, Hyun-woo Lee 0012, Hyun Woo Lee 0012) — Electronic Telecommunication Research Institute (ETRI), Broadcasting and Telecommunications Convergence Research Laboratory, Intelligent Convergence Media Research Department, Daejeon, Korea (and 1 more)
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2010 – 2019
- 2018
[j8]Junyoung Song, Sewook Hwang, Hyun-Woo Lee, Chulwoo Kim:
A 1-V 10-Gb/s/pin Single-Ended Transceiver With Controllable Active-Inductor-Based Driver and Adaptively Calibrated Cascaded-Equalizer for Post-LPDDR4 Interfaces. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(1): 331-342 (2018)- 2017
- [j7]Junyoung Song, Hyun-Woo Lee, Sewook Hwang, Chulwoo Kim:
A 10 Gbits/s/pin DFE-Less Graphics DRAM Interface With Adaptive-Bandwidth PLL for Avoiding Noise Interference and CIJ Reduction Technique. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 344-353 (2017) - 2015
- [c12]Junyoung Song, Hyun-Woo Lee, Jayoung Kim, Sewook Hwang, Chulwoo Kim:
17.6 1V 10Gb/s/pin single-ended transceiver with controllable active-inductor-based driver and adaptively calibrated cascade-DFE for post-LPDDR4 interfaces. ISSCC 2015: 1-3 - 2014
- [b1]Chulwoo Kim, Hyun-Woo Lee, Junyoung Song:
High-Bandwidth Memory Interface. Springer Briefs in Electrical and Computer Engineering, Springer 2014, ISBN 978-3-319-02380-9, pp. i-viii, 1-88 - [j6]Junyoung Song, Sewook Hwang, Hyun-Woo Lee, Chulwoo Kim:
A 7.5-Gb/s Referenceless Transceiver With Adaptive Equalization and Bandwidth-Shifting Technique for Ultrahigh-Definition Television in a 0.13- µm CMOS Process. IEEE Trans. Circuits Syst. II Express Briefs 61-II(11): 865-869 (2014) - [j5]Hyun-Woo Lee, Chulwoo Kim:
Survey and Analysis of Delay-Locked Loops Used in DRAM Interfaces. IEEE Trans. Very Large Scale Integr. Syst. 22(4): 701-711 (2014) - [c11]Hyun-Woo Lee, Junyoung Song, Sangah Hyun, Seunggeun Baek, Yuri Lim, Jungwan Lee, Minsu Park, Haerang Choi, Changkyu Choi, Jin-Youp Cha, Jaeil Kim, Hoon Choi, Seung-Wook Kwack, Yonggu Kang, Jongsam Kim, Junghoon Park, Jonghwan Kim, Jin-Hee Cho, Chulwoo Kim, Yunsaing Kim, Jaejin Lee, Byong-Tae Chung, Sung-Joo Hong:
25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector. ISSCC 2014: 434-435 - 2013
- [j4]Soo-Bin Lim, Hyun-Woo Lee, Junyoung Song, Chulwoo Kim:
A 247 µW 800 Mb/s/pin DLL-Based Data Self-Aligner for Through Silicon via (TSV) Interface. IEEE J. Solid State Circuits 48(3): 711-723 (2013) - [c10]Junyoung Song, Hyun-Woo Lee, Sewook Hwang, Inhwa Jung, Chulwoo Kim:
A 7.5Gb/s referenceless transceiver for UHDTV with adaptive equalization and bandwidth scanning technique in 0.13µm CMOS process. ASP-DAC 2013: 89-90 - [c9]Junyoung Song, Hyun-Woo Lee, Soo-Bin Lim, Sewook Hwang, Yunsaing Kim, Young-Jung Choi, Byong-Tae Chung, Chulwoo Kim:
An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb/s/pin graphics DRAM interface. ISSCC 2013: 312-313 - 2012
- [j3]Hyun-Woo Lee, Ki-Han Kim, Young-Kyoung Choi, Ju-Hwan Sohn, Nak-Kyu Park, Kwan-Weon Kim, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung:
A 1.6 V 1.4 Gbp/s/pin Consumer DRAM With Self-Dynamic Voltage Scaling Technique in 44 nm CMOS Technology. IEEE J. Solid State Circuits 47(1): 131-140 (2012) - [j2]Hyun-Woo Lee, Hoon Choi, Beom-Ju Shin, Kyung-Hoon Kim, Kyung Whan Kim, Jaeil Kim, Kwang Hyun Kim, Jongho Jung, Jae-Hwan Kim, Eun Young Park, Jong-Sam Kim, Jong-Hwan Kim, Jin-Hee Cho, Nam Gyu Rye, Jun Hyun Chun, Yunsaing Kim, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung:
A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces. IEEE J. Solid State Circuits 47(6): 1436-1447 (2012) - [c8]Hyun-Woo Lee, Soo-Bin Lim, Junyoung Song, Jabeom Koo, Dae-Han Kwon, Jong-Ho Kang, Yunsaing Kim, Young-Jung Choi, Kunwoo Park, Byong-Tae Chung, Chulwoo Kim:
A 283.2μW 800Mb/s/pin DLL-based data self-aligner for Through-Silicon Via (TSV) interface. ISSCC 2012: 48-50 - 2011
- [c7]Hyun-Woo Lee, Ki-Han Kim, Young-Kyoung Choi, Ju-Hwan Shon, Nak-Kyu Park, Kwan-Weon Kim, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung:
A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology. ISSCC 2011: 502-504 - 2010
- [c6]Hyun-Woo Lee, Yong-Hoon Kim, Won-Joo Yun, Eun Young Park, Kang Youl Lee, Jaeil Kim, Kwang Hyun Kim, Jongho Jung, Kyung Whan Kim, Nam Gyu Rye, Kwan-Weon Kim, Jun Hyun Chun, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung, Joong Sik Kih:
A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface. ISCAS 2010: 3861-3864
2000 – 2009
- 2009
- [j1]Won-Joo Yun, Hyun-Woo Lee, Dongsuk Shin, Young-Jung Choi, Suki Kim:
Coverage expandable current type code controlled DCC with TDC-based range selector. IEICE Electron. Express 6(5): 205-210 (2009) - [c5]Hyun-Woo Lee, Won-Joo Yun, Young-Kyoung Choi, Hyang-Hwa Choi, Jong-Jin Lee, Ki-Han Kim, Shin-Deok Kang, Ji-Yeon Yang, Jae-Suck Kang, Hyeng-Ouk Lee, Dong-Uk Lee, Sujeong Sim, Young-Ju Kim, Won-Jun Choi, Keun-Soo Song, Sang-Hoon Shin, Hyung-Wook Moon, Seung-Wook Kwack, Jung-Woo Lee, Nak-Kyu Park, Kwan-Weon Kim, Young-Jung Choi, Jin-Hong Ahn, Byong-Tae Chung:
A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS. ISSCC 2009: 140-141 - 2008
- [c4]Dongsuk Shin, Won-Joo Yun, Hyun-Woo Lee, Young-Jung Choi, Suki Kim, Chulwoo Kim:
A 0.17-1.4GHz low-jitter all digital DLL with TDC-based DCC using pulse width detection scheme. ESSCIRC 2008: 82-85 - [c3]Dong-Uk Lee, Shin-Deok Kang, Nak-Kyu Park, Hyun Woo Lee, Young-Kyoung Choi, Jung-Woo Lee, Seung-Wook Kwack, Hyeong-Ouk Lee, Won-Joo Yun, Sang-Hoon Shin, Kwan-Weon Kim, Young-Jung Choi, Ye Seok Yang:
Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface. ISSCC 2008: 280-281 - [c2]Won-Joo Yun, Hyun Woo Lee, Dongsuk Shin, Shin-Deok Kang, Ji-Yeon Yang, Hyeng-Ouk Lee, Dong-Uk Lee, Sujeong Sim, Young-Ju Kim, Won-Jun Choi, Keun-Soo Song, Sang-Hoon Shin, Hyang-Hwa Choi, Hyung-Wook Moon, Seung-Wook Kwack, Jung-Woo Lee, Young-Kyoung Choi, Nak-Kyu Park, Kwan-Weon Kim, Young-Jung Choi, Jin-Hong Ahn, Ye Seok Yang:
A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology. ISSCC 2008: 282-283 - 2006
- [c1]Dong-Uk Lee, Hyun Woo Lee, Ki Chang Kwean, Young-Kyoung Choi, Hyong Uk Moon, Seung-Wook Kwack, Shin-Deok Kang, Kwan-Weon Kim, Yong Ju Kim, Young-Jung Choi, Patrick B. Moran, Jin-Hong Ahn, Joong Sik Kih:
A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL. ISSCC 2006: 547-556
Coauthor Index
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