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ORCIDLibo Huang 0002
Person information
- affiliation: National University of Defense Technology, Changsha, School of Computer, China
Other persons with the same name
- Libo Huang — disambiguation page
- Libo Huang 0001
![[0000-0002-4479-5840]](https://devdomain4test.ir/img/orcid-mark.12x12.png "0000-0002-4479-5840")
— Chinese Academy of Sciences (CAS), Institute of Computing Technology (ICT), Beijing, China (and 1 more) - Libo Huang 0003 — King Abdullah University of Science and Technology (KAUST), Visual Computing Center, Thuwal, Saudi Arabia
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2020 – today
- 2026
[j43]Run Yan, Hui Guo, Libo Huang, Nong Xiao, Li Shen, Yongwen Wang, Yashuai Lv, Gang Chen:
A Survey on Deep Learning for Monte Carlo Path Tracing. ACM Comput. Surv. 58(4): 101:1-101:38 (2026)- [j42]Jianing Zheng, Gang Chen, Libo Huang, Xin Lou, Wei-Shi Zheng:
Terafly: A Multinode FPGA-Based Accelerator Design for Efficient Cooperative Inference in LLMs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 45(5): 2446-2459 (2026) - [c73]Qi Xiong, Renzhi Chen, Zhigang Fang, Bowei Wang, Yingjie Zhou, Libo Huang, Lei Wang:
EstCoder: A RTL Code Generator based on Static Functional Estimation. DATE 2026: 1-3 - [c72]Yanmeng Huang, Ling Yang, Yuanhu Cheng, Junhui Wang, Quan Deng, Junbo Tie, Yongwen Wang, Hai Zhong, Libo Huang:
Vector Value Prediction with Element-wise Stride Compression. ACM Great Lakes Symposium on VLSI 2026: 883-889 - 2025
- [j41]Ling Yang, Libo Huang, Zhenxuan Xiong, Yongwen Wang, Weixia Xu:
EgDiff: An Enhanced Global Load Value Predictor. IEEE Comput. Archit. Lett. 24(2): 241-244 (2025) - [j40]Libo Huang, Jing Zhang, Ling Yang, Sheng Ma, Yongwen Wang, Yuanhu Cheng:
RVAM16: a low-cost multiple-ISA processor based on RISC-V and ARM Thumb. Frontiers Comput. Sci. 19(1): 191103 (2025) - [j39]Ling Yang, Zhong Zheng, Libo Huang, Run Yan, Sheng Ma, Yongwen Wang, Weixia Xu:
Optimizing value prediction for ILP processors: A design space exploration approach. Integr. 103: 102402 (2025) - [j38]Mingxin Tang, Wei Chen, Lizhou Wu, Libo Huang, Kun Zeng:
ChatDSE: A Zero-Shot Microarchitecture Design Space Explorer Powered by GPT4.0. ACM Trans. Design Autom. Electr. Syst. 30(4): 62:1-62:24 (2025) - [c71]Fei Liu, Yanping Shao, Zhouquan Liu, Jing Zhang, Junbo Tie, Mingche Lai, Gang Chen, Libo Huang:
RISC-TAE: Instruction Set Extension for Transformer Model Acceleration. CASES 2025: 23-24 - [c70]Zhouquan Liu, Libo Huang, Ling Yang, Gang Chen, Wei Liu, Mingche Lai, Yongwen Wang:
Late Breaking Results: AFS: Improving Accuracy of Quantized Mamba via Aggressive Forgetting Strategy. DATE 2025: 1-2 - [c69]Zhenxuan Xiong, Libo Huang, Ling Yang, Hui Guo, Junhui Wang, Zhong Zheng, Songwen Pei, Gang Chen, Yongwen Wang:
SONet: Towards Practical Online Neural Network for Enhancing Hard-to-Predict Branches. Euro-Par (2) 2025: 89-102 - [c68]Xin Peng, Pengcheng Li, Gang Chen, Mingche Lai, Lin Deng, Qianmin Yang, Yongwen Wang, Libo Huang:
Low-Cost Approximate Floating-Point Multiplier Design Based on SSA and Sparse Processing. ICA3PP (6) 2025: 112-127 - [c67]Junhui Wang, Jierong Tang, Shiyuan Wang, Yijing Peng, Hongwei Zhou, Quanyou Feng, Libo Huang, Yongwen Wang:
Facess: A Fast Access Method for Shared Data Among Multi-cores in Parallel Programs. ICA3PP (1) 2025: 419-437 - [c66]Ziyi Bo, Nuo Xu, Kang Liu, Anning Zhao, Chenghao Tan, Libo Huang:
HT-DLC: A Data Layout and Computing Design for Logic-in-Memory Convolution with High Throughput. ICA3PP (1) 2025: 519-538 - [c65]Zhenzhen Jia, Hongbing Tan, Ling Yang, Hui Guo, Kun Zeng, Junsheng Chang, Yongwen Wang, Libo Huang:
PolyPE: An Efficient Multi-Precision Multi-Mode Floating-Point Processing Element for HPC and AI. ICCD 2025: 49-56 - [c64]Run Yan, Su Yin, Hui Guo, Yongwen Wang, Gang Chen, Nong Xiao, Libo Huang:
Brief Announcement: LCTree: A Fast Hardware BVH Constructor for Real-Time Ray Tracing. SPAA 2025: 608-612 - 2024
- [j37]Junsheng Chang, Kai Lu, Yang Guo, Yongwen Wang, Zhenyu Zhao, Libo Huang, Hongwei Zhou, Yao Wang, Fei Lei, Biwei Zhang:
A survey of compute nodes with 100 TFLOPS and beyond for supercomputers. CCF Trans. High Perform. Comput. 6(3): 243-262 (2024) - [j36]Yunping Zhao, Sheng Ma, Hengzhu Liu, Libo Huang, Yi Dai:
SAC: An Ultra-Efficient Spin-based Architecture for Compressed DNNs. ACM Trans. Archit. Code Optim. 21(1): 7:1-7:26 (2024) - [j35]Hongbing Tan, Libo Huang, Zhong Zheng, Hui Guo, Qianming Yang, Li Shen, Gang Chen, Liquan Xiao, Nong Xiao:
A Low-Cost Floating-Point Dot-Product-Dual-Accumulate Architecture for HPC-Enabled AI. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(2): 681-693 (2024) - [j34]Hongbing Tan, Jing Zhang, Xiaowei He, Libo Huang, Yongwen Wang, Liquan Xiao:
A Low-Cost Floating-Point FMA Unit Supporting Package Operations for HPC-AI Applications. IEEE Trans. Circuits Syst. II Express Briefs 71(7): 3488-3492 (2024) - [j33]Yunping Zhao, Sheng Ma, Hengzhu Liu, Libo Huang:
EPHA: An Energy-efficient Parallel Hybrid Architecture for ANNs and SNNs. ACM Trans. Design Autom. Electr. Syst. 29(3): 43:1-43:28 (2024) - [j32]Run Yan, Yin Su, Hui Guo, Yashuai Lü, Jin Wang, Nong Xiao, Li Shen, Yongwen Wang, Libo Huang:
MPRTA: An Efficient Multilevel Parallel Mobile Accelerator for High-Performance Ray Tracing. IEEE Trans. Very Large Scale Integr. Syst. 32(2): 396-400 (2024) - [c63]Yude Fang, Junhui Wang, Libo Huang, Yongwen Wang, Weixia Xu:
Out-of-Order and Recursive RAS: A Return Address Stack Design on High Performance Processor. ASAP 2024: 116-117 - [c62]Yin Su, Hui Guo, Run Yan, Yong Wang, Yongwen Wang, Nong Xiao, Gang Chen, Weihua Zhang, Libo Huang:
QuickTree: A Fast Hardware BVH Construction Engine. CF 2024 - [c61]Hongbing Tan, Xiaowei He, Guichu Sun, Liquan Xiao, Yuanhu Cheng, Jing Zhang, Zhong Zheng, Quan Deng, Bingcai Sui, Yongwen Wang, Libo Huang:
ImSPU: Implicit Sharing of Computation Resources Between Vector and Scalar Processing Units. Euro-Par (2) 2024: 77-90 - [c60]Ling Yang, Zhong Zheng, Libo Huang, Run Yan, Sheng Ma, Yongwen Wang, Weixia Xu:
Cost-Effective Value Predictor for ILP processors through Design Space Exploration. ACM Great Lakes Symposium on VLSI 2024: 301-304 - [c59]Ziming Chen, Quan Deng, Yiyue Hu, Xiaowei He, Libo Huang, Yongwen Wang:
SSC: An SRAM-Based Silence Computing Design for On-chip Memory. ICA3PP (4) 2024: 40-59 - [c58]Feichi Han, Mingsong Lv, Libo Huang, Gang Chen:
An Automatic Hardware Generator for CNN Accelerator on FPGA with Efficient Resource Allocation. ICTA 2024: 124-125 - [c57]Songwen Pei, Hongli Ma, Xinyun Qiu, Libo Huang:
DiffSenseNet: Integrating Hierarchical Features and Angular Diffusion for Remote Sensing Object Detection. ISPA 2024: 1096-1101 - [c56]Ling Zhang, Libo Huang, Hui Guo:
Low-Precision Vectorized Arithmetic Unit Designs for Deep Learning. ISVLSI 2024: 794-797 - [c55]Changcai Li, Zonghua Gu, Gang Chen, Libo Huang, Wei Zhang, Huihui Zhou:
Real-time Stereo-based 3D Object Detection for Streaming Perception. NeurIPS 2024 - [i1]Changcai Li, Zonghua Gu, Gang Chen, Libo Huang, Wei Zhang, Huihui Zhou:
Real-time Stereo-based 3D Object Detection for Streaming Perception. CoRR abs/2410.12394 (2024) - 2023
- [j31]Run Yan, Libo Huang, Hui Guo, Yashuai Lü, Ling Yang, Nong Xiao, Li Shen, Mengqiao Lan, Yongwen Wang:
MMsRT: A Hardware Architecture for Ray Tracing in the Mobile Domain. J. Circuits Syst. Comput. 32(11): 2350192:1-2350192:14 (2023) - [j30]Hongbing Tan, Gan Tong, Libo Huang, Liquan Xiao, Nong Xiao:
Multiple-Mode-Supporting Floating-Point FMA Unit for Deep Learning Processors. IEEE Trans. Very Large Scale Integr. Syst. 31(2): 253-266 (2023) - [c54]Hongbing Tan, Jing Zhang, Libo Huang, Xiaowei He, Dezun Dong, Yongwen Wang, Liquan Xiao:
A Multi-level Parallel Integer/Floating-Point Arithmetic Architecture for Deep Learning Instructions. Euro-Par 2023: 260-274 - [c53]Jing Zhang, Libo Huang, Hongbing Tan, Ling Yang, Zhong Zheng, Qianming Yang:
Low-Cost Multiple-Precision Multiplication Unit Design For Deep Learning. ACM Great Lakes Symposium on VLSI 2023: 9-14 - [c52]Jing Zhang, Libo Huang, Hongbing Tan, Zhong Zheng, Hui Guo:
A Scalable BFloat16 Dot-Product Architecture for Deep Learning. ACM Great Lakes Symposium on VLSI 2023: 219-220 - [c51]Ling Yang, Libo Huang, Zhong Zheng:
Confidence Counter Modelling for Value Predictor. ACM Great Lakes Symposium on VLSI 2023: 221-222 - [c50]Jing Zhang, Hongbing Tan, Libo Huang:
SFDoP: A Scalable Fused BFloat16 Dot-Product Architecture for DNN. ICCD 2023: 62-65 - 2022
- [j29]Ling Yang, Libo Huang, Run Yan, Nong Xiao, Sheng Ma, Li Shen, Weixia Xu:
Stride Equality Prediction for Value Speculation. IEEE Comput. Archit. Lett. 21(2): 57-60 (2022) - [j28]Yuanhu Cheng, Libo Huang, Yi-Jun Cui, Sheng Ma, Yongwen Wang, Bingcai Sui:
RV16: An Ultra-Low-Cost Embedded RISC-V Processor Core. J. Comput. Sci. Technol. 37(6): 1307-1319 (2022) - [c49]Run Yan, Libo Huang, Hui Guo, Yashuai Lü, Ling Yang, Nong Xiao, Li Shen, Yongwen Wang:
RTA: an Efficient SIMD Architecture for Ray Tracing. HPCC/DSS/SmartCity/DependSys 2022: 43-50 - [c48]Wei Jiang, Bo Wang, Sheng Ma, Xiang Hou, Libo Huang, Yi Dai, Jianbin Fang:
PipeFB: An Optimized Pipeline Parallelism Scheme to Reduce the Peak Memory Usage. ICA3PP 2022: 590-604 - [c47]Hongbing Tan, Run Yan, Ling Yang, Libo Huang, Liquan Xiao, Qianming Yang:
Efficient Multiple-Precision and Mixed-Precision Floating-Point Fused Multiply-Accumulate Unit for HPC and AI Applications. ICA3PP 2022: 642-659 - [c46]Gan Tong, Run Yan, Ling Yang, Mengqiao Lan, Jing Zhang, Yuanhu Cheng, Wentao Ma, Yashuai Lü, Sheng Ma, Libo Huang:
Optimizing Winograd Convolution on GPUs via Partial Kernel Fusion. NPC 2022: 17-29 - [c45]Bo Wang, Sheng Ma, Zhong Liu, Libo Huang, Yuan Yuan, Yi Dai:
SADD: A Novel Systolic Array Accelerator with Dynamic Dataflow for Sparse GEMM in Deep Learning. NPC 2022: 42-53 - 2021
- [j27]Xiaogang Jia, Wei Chen, Zhengfa Liang, Xin Luo, Mingfei Wu, Chen Li, Yulin He, Yusong Tan, Libo Huang:
A Joint 2D-3D Complementary Network for Stereo Matching. Sensors 21(4): 1430 (2021) - [j26]Yulin He, Wei Chen, Chen Li, Xin Luo, Libo Huang:
Fast and Accurate Lane Detection via Graph Structure and Disentangled Representation Learning. Sensors 21(14): 4657 (2021) - [j25]Ya-Shuai Lü, Hui Guo, Libo Huang, Qi Yu, Li Shen, Nong Xiao, Zhiying Wang:
GraphPEG: Accelerating Graph Processing on GPUs. ACM Trans. Archit. Code Optim. 18(3): 30:1-30:24 (2021) - [c44]Xiaogang Jia, Wei Chen, Zhengfa Liang, Xin Luo, Mingfei Wu, Yusong Tan, Libo Huang:
Multi-Scale Cascade Disparity Refinement Stereo Network. ICASSP 2021: 2110-2114 - [c43]Xiaogang Jia, Wei Chen, Chen Li, Zhengfa Liang, Mingfei Wu, Yusong Tan, Libo Huang:
Multi-Scale Cost Volumes Cascade Network for Stereo Matching. ICRA 2021: 8657-8663 - 2020
- [j24]Kang Jin, Dezun Dong, Cunlu Li, Libo Huang, Sheng Ma, Binzhang Fu:
DancerFly: An Order-Aware Network-on-Chip Router On-the-Fly Mitigating Multi-path Packet Reordering. Int. J. Parallel Program. 48(4): 730-749 (2020) - [j23]Qi Yu, Bruce R. Childers, Libo Huang, Cheng Qian, Zhiying Wang:
HPE: Hierarchical Page Eviction Policy for Unified Memory in GPUs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2461-2474 (2020) - [j22]Qi Yu, Bruce R. Childers, Libo Huang, Cheng Qian, Zhiying Wang:
A quantitative evaluation of unified memory in GPUs. J. Supercomput. 76(4): 2958-2985 (2020) - [c42]Qi Yu, Bruce R. Childers, Libo Huang, Cheng Qian, Hui Guo, Zhiying Wang:
Coordinated Page Prefetch and Eviction for Memory Oversubscription Management in GPUs. IPDPS 2020: 472-482
2010 – 2019
- 2019
- [j21]Sheng Ma, Yuanwu Lei, Libo Huang, Zhiying Wang:
MT-DMA: A DMA Controller Supporting Efficient Matrix Transposition for Digital Signal Processing. IEEE Access 7: 5808-5818 (2019) - [j20]Libo Huang, Ya-Shuai Lü, Sheng Ma, Nong Xiao, Zhiying Wang:
SIMD stealing: Architectural support for efficient data parallel execution on multicores. Microprocess. Microsystems 65: 136-147 (2019) - [j19]Libo Huang, Qi Yu, Chaobing Zhou, Jianqiao Ma, Zhisheng Li, Qiang Dou:
Efficient architectural exploration of TAGE branch predictor for embedded processors. Microelectron. J. 88: 88-98 (2019) - [j18]Sheng Ma, Zhong Liu, Shenggang Chen, Libo Huang, Yang Guo, Zhiying Wang, Meidi Zhang:
Coordinated DMA: Improving the DRAM Access Efficiency for Matrix Multiplication. IEEE Trans. Parallel Distributed Syst. 30(10): 2148-2164 (2019) - [c41]Sheng Ma, Yang Guo, Shenggang Chen, Libo Huang, Zhiying Wang:
Improving the DRAM Access Efficiency for Matrix Multiplication on Multicore Accelerators. DATE 2019: 1058-1063 - [c40]Sheng Ma, Libo Huang, Yuanwu Lei, Yang Guo, Zhiying Wang:
An Efficient Direct Memory Access (DMA) Controller for Scientific Computing Accelerators. ISCAS 2019: 1-5 - [c39]Qi Yu, Bruce R. Childers, Libo Huang, Cheng Qian, Zhiying Wang:
Hierarchical Page Eviction Policy for Unified Memory in GPUs. ISPASS 2019: 149-150 - 2018
- [j17]Hui Guo, Libo Huang, Ya-Shuai Lü, Sheng Ma, Zhiying Wang:
DyCache: Dynamic Multi-Grain Cache Management for Irregular Memory Accesses on GPU. IEEE Access 6: 38881-38891 (2018) - [j16]Hui Guo, Libo Huang, Ya-Shuai Lü, Jianqiao Ma, Cheng Qian, Sheng Ma, Zhiying Wang:
Accelerating BFS via Data Structure-Aware Prefetching on GPU. IEEE Access 6: 60234-60248 (2018) - [j15]Wenjie Liu, Sheng Ma, Libo Huang, Zhiying Wang:
The Design of NoC-Side Memory Access Scheduling for Energy-Efficient GPGPUs. Int. J. Parallel Program. 46(4): 722-735 (2018) - [j14]Qi Yu, Libo Huang, Cheng Qian, Jianqiao Ma, Zhiying Wang:
FC-AMAT: factor-based C-AMAT analysis in memory system measurement. Innov. Syst. Softw. Eng. 14(2): 143-156 (2018) - [j13]Cheng Qian, Libo Huang, Qi Yu, Zhiying Wang:
CHAM: Improving Prefetch Efficiency Using a Composite Hierarchy-Aware Method. J. Circuits Syst. Comput. 27(7): 1850114:1-1850114:34 (2018) - [j12]Xiangke Liao, Kai Lu, Canqun Yang, Jin-wen Li, Yuan Yuan, Ming-che Lai, Libo Huang, Pingjing Lu, Jianbin Fang, Jing Ren, Jie Shen:
Moving from exascale to zettascale computing: challenges and techniques. Frontiers Inf. Technol. Electron. Eng. 19(10): 1236-1244 (2018) - [c38]Cheng Qian, Libo Huang, Qi Yu, Zhiying Wang, Bruce R. Childers:
CMH: compression management for improving capacity in the hybrid memory cube. CF 2018: 121-128 - [c37]Xin Zhang, Libo Huang, Zhiying Wang, Qi Yu:
Peer-Formulated Assignment Method for Experimental Projects in CS courses. FIE 2018: 1-8 - [c36]Ximing He, Sheng Ma, Wenjie Liu, Sijiang Fan, Libo Huang, Zhiying Wang, Zhanyong Zhou:
VISU: A Simple and Efficient Cache Coherence Protocol Based on Self-updating. ICA3PP (4) 2018: 341-357 - [c35]Sheng Ma, Hongyi Lu, Libo Huang, Li Shen, Yang Guo, Zhiying Wang, Wenliang Xue:
Adaptive VC Partitioning for NoCs in GPGPUs. ISCAS 2018: 1-5 - [c34]Qi Yu, Libo Huang, Hui Guo, Cheng Qian, Sheng Ma, Zhiying Wang:
Improving Branch Prediction Accuracy on Multi-Core Architectures for Big Data. ISPA/IUCC/BDCloud/SocialCom/SustainCom 2018: 377-382 - [c33]Cheng Qian, Bruce R. Childers, Libo Huang, Qi Yu, Zhiying Wang:
HMCSP: Reducing Transaction Latency of CSR-based SPMV in Hybrid Memory Cube. ISPASS 2018: 114-116 - [c32]Qi Yu, Libo Huang, Cheng Qian, Jianqiao Ma, Zhiying Wang:
Evaluating Memory Performance of Emerging Scale-Out Applications Using C-AMAT. ISPASS 2018: 117-119 - 2017
- [j11]Libo Huang, Ya-Shuai Lü, Li Shen, Zhiying Wang:
Improving the Efficiency of GPGPU Work-Queue Through Data Awareness. ACM Trans. Archit. Code Optim. 14(4): 45:1-45:22 (2017) - [c31]Ya-Shuai Lü, Libo Huang, Li Shen:
POSTER: DaQueue: A Data-Aware Work-Queue Design for GPGPUs. PACT 2017: 142-143 - [c30]Qi Yu, Libo Huang, Cheng Qian, Zhiying Wang:
BC-AMAT: Considering Blocked Time in Memory System Measurement. Conf. Computing Frontiers 2017: 230-236 - [c29]Chaobing Zhou, Libo Huang, Zhisheng Li, Tan Zhang, Qiang Dou:
Design Space Exploration of TAGE Branch Predictor with Ultra-Small RAM. ACM Great Lakes Symposium on VLSI 2017: 281-286 - [c28]Jianqiao Ma, Qi Yu, Libo Huang, Cheng Qian, Zhiying Wang:
Trace-based method for big data memory characteristics research. ICACCI 2017: 1023-1027 - [c27]Chaobing Zhou, Libo Huang, Tan Zhang, Yongwen Wang, Chengyi Zhang, Qiang Dou:
Effective Optimization of Branch Predictors through Lightweight Simulation. ICCD 2017: 653-656 - [c26]Ya-Shuai Lü, Libo Huang, Li Shen, Zhiying Wang:
Unleashing the power of GPU for physically-based rendering via dynamic ray shuffling. MICRO 2017: 560-573 - [c25]Chaobing Zhou, Libo Huang, Qiang Dou:
BPSim: An integrated missrate, area, and power simulator for branch predictor. MOCAST 2017: 1-4 - [c24]Tan Zhang, Chaobing Zhou, Libo Huang, Nong Xiao:
Branch Prediction Migration for Multi-Core Architectures. NAS 2017: 1-2 - [c23]Chaobing Zhou, Libo Huang, Zhisheng Li, Qiang Dou:
SimpleBP: A Lightweight Branch Prediction Simulator for Effective Design Exploration. NAS 2017: 1-2 - [c22]Tan Zhang, Chaobing Zhou, Libo Huang, Nong Xiao, Sheng Ma:
Improving Branch Prediction for Thread Migration on Multi-core Architectures. NPC 2017: 87-99 - [c21]Xin Zhang, Jinfeng Huang, Libo Huang, Zhiying Wang:
Motivating Students through Peer-Formulated Assignments in CS Experimental Courses. SIGITE 2017: 181 - [c20]Qi Yu, Libo Huang, Cheng Qian, Jianqiao Ma, Zhiying Wang:
Factor-Based C-AMAT Analysis for Memory Optimization. VECoS 2017: 79-91 - 2016
- [c19]Yongwen Wang, Libo Huang, Zhong Zheng:
A Methodology for Performance Verification of Microprocessors. NCCET 2016: 24-31 - 2015
- [c18]Libo Huang, Yongwen Wang, Qiang Dou, Chengyi Zhang, Caixia Sun, Chao Xu:
Fast FPGA system for microarchitecture optimization on synthesizable modern processor design. FPL 2015: 1-4 - [c17]Cheng Qian, Libo Huang, Peng Xie, Nong Xiao, Zhiying Wang:
A Study on Non-volatile 3D Stacked Memory for Big Data Applications. ICA3PP (1) 2015: 103-118 - [c16]Cheng Qian, Libo Huang, Peng Xie, Nong Xiao, Zhiying Wang:
Efficient data management on 3D stacked memory for big data applications. IDT 2015: 84-89 - 2014
- [j10]Libo Huang, Zhiying Wang, Nong Xiao, Qiang Dou:
Efficient Utilization of SIMD Engines for General-Purpose Processors. Comput. J. 57(8): 1141-1154 (2014) - [j9]Libo Huang, Li Shen, Yashuai Lv, Zhiying Wang, Kui Dai:
Mac or Non-MAC: not a Problem. J. Circuits Syst. Comput. 23(5) (2014) - [j8]Sheng Ma, Natalie D. Enright Jerger, Zhiying Wang, Ming-che Lai, Libo Huang:
Holistic Routing Algorithm Design to Support Workload Consolidation in NoCs. IEEE Trans. Computers 63(3): 529-542 (2014) - [j7]Libo Huang, Zhiying Wang, Nong Xiao, Yongwen Wang, Qiang Dou:
Integrated Coherence Prediction: Towards Efficient Cache Coherence on NoC-Based Multicore Architectures. ACM Trans. Design Autom. Electr. Syst. 19(3): 24:1-24:22 (2014) - [c15]Libo Huang:
Leveraging on-chip networks for efficient prediction on multicore coherence. DATE 2014: 1-4 - 2013
- [j6]Libo Huang, Zhiying Wang, Nong Xiao:
VBON: Toward efficient on-chip networks via hierarchical virtual bus. Microprocess. Microsystems 37(8-B): 915-928 (2013) - [j5]Libo Huang, Nong Xiao, Zhiying Wang, Yongwen Wang, Ming-che Lai:
Efficient multimedia coprocessor with enhanced SIMD engines for exploiting ILP and DLP. Parallel Comput. 39(10): 586-602 (2013) - [j4]Libo Huang, Zhiying Wang, Nong Xiao, Yongwen Wang, Qiang Dou:
Adaptive communication mechanism for accelerating MPI functions in NoC-based multicore processors. ACM Trans. Archit. Code Optim. 10(3): 18:1-18:25 (2013) - [j3]Libo Huang, Zhiying Wang, Nong Xiao, Yongwen Wang, Qiang Dou:
Dynamic Streamization Model Execution for SIMD Engines on Multicore Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(11): 1814-1818 (2013) - [c14]Bo Su, Li Shen, Lei Wang, Zhiying Wang, Yourui Wang, Libo Huang, Wei Shi:
DCP: Improving the Throughput of Asynchronous Pipeline by Dual Control Path. HPCC/EUC 2013: 230-237 - 2012
- [j2]Libo Huang, Sheng Ma, Li Shen, Zhiying Wang, Nong Xiao:
Low-Cost Binary128 Floating-Point FMA Unit Design with SIMD Support. IEEE Trans. Computers 61(5): 745-751 (2012) - [c13]Libo Huang, Zhiying Wang, Nong Xiao:
Accelerating NoC-Based MPI Primitives via Communication Architecture Customization. ASAP 2012: 141-148 - [c12]Libo Huang, Zhiying Wang, Nong Xiao:
An optimized multicore cache coherence design for exploiting communication locality. ACM Great Lakes Symposium on VLSI 2012: 59-62 - 2011
- [c11]Libo Huang, Zhiying Wang, Li Shen, Hongyi Lu, Nong Xiao, Cong Liu:
A specialized low-cost vectorized loop buffer for embedded processors. DATE 2011: 1200-1203 - 2010
- [c10]Libo Huang, Li Shen, Zhiying Wang, Wei Shi, Nong Xiao, Sheng Ma:
SIF: Overcoming the limitations of SIMD devices via implicit permutation. HPCA 2010: 1-12 - [c9]Libo Huang, Zhiying Wang:
SV: Enhancing SIMD Architectures via Combined SIMD-Vector Approach. ICA3PP (1) 2010: 226-235 - [c8]Libo Huang, Li Shen, Zhiying Wang:
Permutation optimization for SIMD devices. ISCAS 2010: 3849-3852
2000 – 2009
- 2009
- [j1]Ya-Shuai Lü, Li Shen, Libo Huang, Zhiying Wang, Nong Xiao:
Optimal subgraph covering for customisable VLIW processors. IET Comput. Digit. Tech. 3(1): 14-23 (2009) - [c7]Sheng Ma, Libo Huang, Zhiying Wang, Kui Dai:
Implementation of OpenVG Path and Paint Algorithms on Synchronous Data Triggered Architecture with Optimization. NAS 2009: 379-385 - 2008
- [c6]Jianjun Guo, Ming-che Lai, Zhengyuan Pang, Libo Huang, Fangyuan Chen, Kui Dai, Zhiying Wang:
Memory System Design for a Multi-core Processor. CISIS 2008: 601-606 - [c5]Ya-Shuai Lü, Li Shen, Libo Huang, Zhiying Wang, Nong Xiao:
Customizing computation accelerators for extensible multi-issue processors with effective optimization techniques. DAC 2008: 197-200 - [c4]Xinbiao Gan, Kui Dai, Libo Huang, Li Shen, Zhiying Wang:
A New CORDIC Algorithm and Software Implementation Based on Synchronized Data Triggering Architecture. MUE 2008: 83-86 - [c3]Jianjun Guo, Ming-che Lai, Zhengyuan Pang, Libo Huang, Fangyuan Chen, Kui Dai, Zhiying Wang:
Hierarchical memory system design for a heterogeneous multi-core processor. SAC 2008: 1504-1508 - 2007
- [c2]Libo Huang, Li Shen, Kui Dai, Zhiying Wang:
A New Architecture For Multiple-Precision Floating-Point Multiply-Add Fused Unit Design. IEEE Symposium on Computer Arithmetic 2007: 69-76 - [c1]Libo Huang, Ming-che Lai, Kui Dai, Hong Yue, Li Shen:
Hardware Support for Arithmetic Units of Processor with Multimedia Extension. MUE 2007: 633-637
Coauthor Index
[j25] [j23] [j22] [c42] [j21] [j20] [j18] [c41] [c40] [c39] [j17] [j16] [j15] [j14] [j13] [c38] [c37] [c36] [c35] [c34] [c33] [c32] [j11] [c30] [c28] [c26] [c21] [c20] [c17] [c16] [j10] [j9] [j8] [j7] [j6] [j5] [j4] [j3] [c14] [j2] [c13] [c12] [c11] [c10] [c9] [c8] [j1] [c7] [c6] [c5] [c4] [c3] [c2]
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Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2026-06-21 23:06 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
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since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
