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ORCIDLinda E. M. Brackenbury
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Journal Articles
- 2010
[j5]Wei Shao, Linda E. M. Brackenbury:
Early stopping turbo decoders: a high-throughput, low-energy bit-level approach and implementation. IET Commun. 4(17): 2115-2124 (2010)- [j4]Linda E. M. Brackenbury, Luis A. Plana
, Jeffrey Pepper:
System-on-Chip Design and Implementation. IEEE Trans. Educ. 53(2): 272-281 (2010) - 2007
- [j3]Linda E. M. Brackenbury, Wei Shao:
Lowering power in an experimental RISC processor. Microprocess. Microsystems 31(5): 360-368 (2007) - 2002
- [j2]Mike J. G. Lewis, Linda E. M. Brackenbury:
CADRE: An Asynchronous Embedded DSP for Mobile Phone Applications. Des. Autom. Embed. Syst. 6(4): 451-475 (2002) - 2001
- [j1]Mike J. G. Lewis, Linda E. M. Brackenbury:
CADRE: A Low-power, Low-EMI DSP Architecture for Digital Mobile Phones. VLSI Design 12(3): 333-348 (2001)
Conference and Workshop Papers
- 2008
- [c7]Wei Shao, Linda E. M. Brackenbury:
Pre-processing of convolutional codes for reducing decoding power consumption. ICASSP 2008: 2957-2960 - 2007
- [c6]Wei Shao, Linda E. M. Brackenbury:
No-Handshake Asynchronous Survivor Memory Unit for a Viterbi Decoder. ICECS 2007: 729-734 - 2004
- [c5]Aristides Efthymiou, W. Suntiamorntut, Jim D. Garside, L. E. M. Brackenbury:
An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm. ASYNC 2004: 207-215 - 2001
- [c4]Mike J. G. Lewis, L. E. M. Brackenbury:
Exploiting Typical DSP Data Access Patterns and Asynchrony for a Low Power Multiported Register Bank. ASYNC 2001: 4-14 - [c3]Peter A. Riocreux, L. E. M. Brackenbury, J. Mike Cumpstey, Stephen B. Furber:
A Low-Power Self-Timed Viterbi Decoder. ASYNC 2001: 15-24 - 2000
- [c2]Mike J. G. Lewis, L. E. M. Brackenbury:
An Instruction Buffer for a Low-Power DSP. ASYNC 2000: 176- - 1999
- [c1]Mike J. G. Lewis, Jim D. Garside, L. E. M. Brackenbury:
Reconfigurable Latch Controllers for Low Power Asynchronous Circuits. ASYNC 1999: 27-35
Coauthor Index
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