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ORCIDZeeshan Ali 0005
Person information
- affiliation: University of Glasgow, James Watt School of Engineering, UK
Other persons with the same name
- Zeeshan Ali — disambiguation page
- Zeeshan Ali 0001
![[0009-0008-8101-9016]](https://devdomain4test.ir/img/orcid-mark.12x12.png "0009-0008-8101-9016")
— University of Bordeaux, CNRS, France - Zeeshan Ali 0002 — National University of Computer and Emerging Sciences, Islamabad, Pakistan
- Zeeshan Ali 0003 — International Islamic University Islamabad, Department of Computer Science, Pakistan
- Zeeshan Ali 0004 — Monash University Malaysia, School of Science, Selangor, Malaysia
- Zeeshan Ali 0006 — National Yunlin University of Science and Technology, Douliou, Taiwan
- Zeeshan Ali 0007 — International Islamic University Islamabad, Department of Mathematics and Statistics, Pakistan
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2020 – today
- 2025
[j4]Hossein Eslahi, Stavroula Kapoulea, Zeeshan Ali, Mohammed Waqas Mughal, Farman Ullah, Meraj Ahmad, Martin Weides, Hadi Heidari:
De-Embedding Methodology to Characterize Linearity of Active Filters Under Process Variations. IEEE Trans. Very Large Scale Integr. Syst. 33(5): 1462-1466 (2025)- [c3]Stavroula Kapoulea, Hossein Eslahi, Zeeshan Ali, Mohammed Waqas Mughal, Meraj Ahmad, Martin Weides, Hadi Heidari:
Cryo-CMOS 0.432mW UHF Filter for Scalable Quantum Computing in 22nm FD-SOI Technology. ISCAS 2025: 1-5 - 2024
- [j3]Zeeshan Ali, Mostafa Elsayed, Girish Tiwari, Meraj Ahmad, Julien Le Kernec, Hadi Heidari, Shalabh Gupta:
Impact of Receiver Thermal Noise and PLL RMS Jitter in Radar Measurements. IEEE Trans. Instrum. Meas. 73: 1-10 (2024) - 2023
- [j2]Zeeshan Ali, Pallavi Paliwal, Phani Raj, Deepak Anand, Debasattam Pal, Shalabh Gupta:
Stability Analysis for Fast Settling Switched Digital Phase-Locked Loops (DPLLs). IEEE Control. Syst. Lett. 7: 1393-1398 (2023) - 2022
- [c2]Zeeshan Ali, Pallavi Paliwal, Rupesh Lad, Dhanraj Bhukya, Shalabh Gupta:
A Fast Locking Ring Oscillator Based Fractional-N DPLL With an Assistance From a LUT-Based FSM. ISCAS 2022: 2745-2749 - 2020
- [j1]Pallavi Paliwal, Vivek Yadav, Zeeshan Ali, Shalabh Gupta:
A Fast Settling Fractional-N DPLL With Loop-Order Switching. IEEE Trans. Very Large Scale Integr. Syst. 28(3): 714-725 (2020) - [c1]Zeeshan Ali, Makwana Harshit R, Shalabh Gupta:
A Low Jitter Double-Tailed Strong-Arm Latch Based Digital-to-Time Converter (DTC). ICECS 2020: 1-4
Coauthor Index
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