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ORCIDTaiquan Wei
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2020 – today
- 2026
[j2]Huizheng Wang
, Taiquan Wei, Hongbin Wang, Zichuan Wang, Xinru Tang, Zhiheng Yue, Shaojun Wei, Yang Hu, Shouyi Yin:
Designing Spatial Architectures for Sparse Attention: STAR Accelerator via Cross-Stage Tiling. IEEE Trans. Computers 75(3): 1125-1140 (2026)- [c7]Xinru Tang, Jingxiang Hou, Dingcheng Jiang, Taiquan Wei, Jiaxin Liu, Jinyi Deng, Huizheng Wang, Qize Yang, Haoran Shang, Chao Li, Yang Hu, Shouyi Yin:
MoEntwine: Unleashing the Potential of Wafer-Scale Chips for Large-Scale Expert Parallel Inference. HPCA 2026: 1-15 - [c6]Huizheng Wang, Zichuan Wang, Hongbin Wang, Jingxiang Hou, Taiquan Wei, Chao Li, Yang Hu, Shouyi Yin:
WATOS: Efficient LLM Training Strategies and Architecture Co-Exploration for Wafer-Scale Chip. HPCA 2026: 1-19 - [c5]Huizheng Wang, Taiquan Wei, Zichuan Wang, Dingcheng Jiang, Qize Yang, Jiaxin Liu, Jingxiang Hou, Chao Li, Jinyi Deng, Yang Hu, Shouyi Yin:
TEMP: A Memory Efficient Physical-Aware Tensor Partition-Mapping Framework on Wafer-Scale Chips. HPCA 2026: 1-18 - 2025
- [j1]Huizheng Wang, Hongbin Wang, Zhiheng Yue, Jingyao Liu, Taiquan Wei, Shaojun Wei, Yang Hu, Shouyi Yin:
BETA: A Bit-Grained Transformer Attention Accelerator With Efficient Early Termination. IEEE Trans. Circuits Syst. II Express Briefs 72(10): 1433-1437 (2025) - [c4]Qize Yang, Jiaxin Liu, Taiquan Wei, Yuxin Jin, Shouyi Yin, Yang Hu:
Segmentation-Aware Optimization of Collective for Waferscale Chips. APPT 2025: 34-46 - [c3]Taiquan Wei, Huizheng Wang, Zichuan Wang, Shouyi Yin, Yang Hu:
Spatial-Aware Orchestration of LLM Attention on Waferscale Chips. APPT 2025: 386-391 - [c2]Qize Yang, Taiquan Wei, Sihan Guan, Chengran Li, Haoran Shang, Jinyi Deng, Huizheng Wang, Chao Li, Lei Wang, Yan Zhang, Shouyi Yin, Yang Hu:
PD Constraint-aware Physical/Logical Topology Co-Design for Network on Wafer. ISCA 2025: 49-64 - [c1]Huizheng Wang, Zichuan Wang, Zhiheng Yue, Yousheng Long, Taiquan Wei, Jianxun Yang, Yang Wang, Chao Li, Shaojun Wei, Yang Hu, Shouyi Yin:
MCBP: A Memory-Compute Efficient LLM Inference Accelerator Leveraging Bit-Slice-enabled Sparsity and Repetitiveness. MICRO 2025: 1592-1608 - [i4]Huizheng Wang, Zichuan Wang, Zhiheng Yue, Yousheng Long, Taiquan Wei, Jianxun Yang, Yang Wang, Chao Li, Shaojun Wei, Yang Hu, Shouyi Yin:
MCBP: A Memory-Compute Efficient LLM Inference Accelerator Leveraging Bit-Slice-enabled Sparsity and Repetitiveness. CoRR abs/2509.10372 (2025) - [i3]Xinru Tang, Jingxiang Hou, Dingcheng Jiang, Taiquan Wei, Jiaxin Liu, Jinyi Deng, Huizheng Wang, Qize Yang, Haoran Shang, Chao Li, Yang Hu, Shouyi Yin:
MoEntwine: Unleashing the Potential of Wafer-scale Chips for Large-scale Expert Parallel Inference. CoRR abs/2510.25258 (2025) - [i2]Huizheng Wang, Taiquan Wei, Zichuan Wang, Dingcheng Jiang, Qize Yang, Jiaxin Liu, Jingxiang Hou, Chao Li, Jinyi Deng, Yang Hu, Shouyi Yin:
TEMP: A Memory Efficient Physical-aware Tensor Partition-Mapping Framework on Wafer-scale Chips. CoRR abs/2512.14256 (2025) - [i1]Huizheng Wang, Taiquan Wei, Hongbin Wang, Zichuan Wang, Xinru Tang, Zhiheng Yue, Shaojun Wei, Yang Hu, Shouyi Yin:
Designing Spatial Architectures for Sparse Attention: STAR Accelerator via Cross-Stage Tiling. CoRR abs/2512.20198 (2025)
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