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Jinwei Tang
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[c2]Nuo Xu
, Jinwei Tang
, Zihang Chen
, Xiaolin Xu
, Wujie Wen
, Zhenman Fang
, Caiwen Ding
:
Privacy-Preserving Constrained Evaluation of LLM-Generated HLS C/C++. ACM Great Lakes Symposium on VLSI 2026: 247-252
[i4]Pengju Liu, Nuo Xu, Jinwei Tang, Yu Cao, Caiwen Ding:
Bridging the Last Mile of Circuit Design: PostEDA-Bench, a Hierarchical Benchmark for PPA Convergence and DRC Fixing. CoRR abs/2605.06936 (2026)- 2025
[c1]Jinwei Tang, Jiayin Qin, Nuo Xu, Pragnya Sudershan Nalla, Yu Cao, Yang Katie Zhao, Caiwen Ding:
MAHL: Multi-Agent LLM-Guided Hierarchical Chiplet Design with Adaptive Debugging. ICCAD 2025: 1-9
[i3]Jinwei Tang, Jiayin Qin, Nuo Xu, Pragnya Sudershan Nalla, Yu Cao, Yang Zhao, Caiwen Ding:
MAHL: Multi-Agent LLM-Guided Hierarchical Chiplet Design with Adaptive Debugging. CoRR abs/2508.14053 (2025)
[i2]Nuo Xu, Zhaoting Gong, Ran Ran, Jinwei Tang, Wujie Wen, Caiwen Ding:
FHE-Agent: Automating CKKS Configuration for Practical Encrypted Inference via an LLM-Guided Agentic Framework. CoRR abs/2511.18653 (2025)- 2024
[i1]Jinwei Tang, Jiayin Qin, Kiran Thorat, Chen Tian, Yu Cao, Yang Zhao, Caiwen Ding:
HiVeGen - Hierarchical LLM-based Verilog Generation for Scalable Chip Design. CoRR abs/2412.05393 (2024)
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