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2020 – today
- 2026
[j17]Hwaseok Shin
, Yoonjae Choi, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Junseob So, Seon-Been Lee, Taehwan Kim, Chulwoo Kim:
A 15-Gb/s PAM-3 Transceiver With Hybrid Equalization and Time-Domain Decoder for High-Bandwidth-Memory Interfaces. IEEE J. Solid State Circuits 61(1): 305-317 (2026)- [j16]Seongcheol Kim, Changmin Sim, Seungwoo Park, Junseob So, Hwaseok Shin, Taewhan Kim, Seon-Been Lee, Chulwoo Kim:
A 20-Gb/s/pin 0.42-pJ/b Single-Ended Receiver With Ping-Pong Self-Referencing Technique. IEEE Trans. Circuits Syst. II Express Briefs 73(4): 438-442 (2026) - 2025
- [j15]Seungwoo Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Hyunsu Park, Youngwook Kwon, Changmin Sim, Seongcheol Kim, Chulwoo Kim:
A 52-Gb/s Low-Power PAM-4 Baud-Rate CDR Using Pattern-Based Phase Detector for Short-Reach Applications. IEEE J. Solid State Circuits 60(8): 2794-2806 (2025) - [j14]Woojin Lee, Changmin Sim, Changjoo Kim, Jinwoo Jeon, Hyundo Jung, Taihyun Kim, Chulwoo Kim:
A 38.1 fJ/Bit Capacitive-Latch True Random Number Generator Featuring Both Autozeroed Inverter Mismatch and Accelerated Evaluation. IEEE Solid State Circuits Lett. 8: 265-268 (2025) - [j13]Jincheol Sim, Changmin Sim, Jonghyuck Choi, Seungwoo Park, Seongcheol Kim, Chulwoo Kim:
A 50 Gb/s PAM-4 Transceiver With High-Swing Driver, Dual-Loop Analog Equalizer, and Integrator-Based Baud-Rate Linear CDR for Short-Reach Links. IEEE Trans. Circuits Syst. I Regul. Pap. 72(4): 1598-1608 (2025) - [j12]Taehwan Kim, Changmin Sim, Seungwoo Park, Jinwoo Park, Seongcheol Kim, Hwaseok Shin, Junseob So, Seonbeen Lee, Youngwook Kwon, Chulwoo Kim:
A 10 Gb/s Single-Ended Receiver Using Time Gap Sense Amplifier for Next-Generation HBM. IEEE Trans. Circuits Syst. II Express Briefs 72(2): 369-373 (2025) - [j11]Hwaseok Shin, Hyoshin Kang, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Junseob So, Taehwan Kim, Chulwoo Kim:
A 28-Gb/s Single-Ended PAM-4 Transceiver With Active-Inductor Equalizer and Amplitude- Detection LSB Decoder for Memory Interfaces. IEEE Trans. Very Large Scale Integr. Syst. 33(3): 662-672 (2025) - [c1]Junseob So, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Hwaseok Shin, Seonbeen Lee, Taehwan Kim, Chulwoo Kim:
22.5 A 0.3pJ/b 32Gb/s/Pin Single-Ended PAM-4 Receiver with a Delay-Less Capacitive-Feedback Equalizer. ISSCC 2025: 1-3 - 2024
- [j10]Jonghyuck Choi, Yoonjae Choi, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Chulwoo Kim:
A Single-Ended NRZ Receiver With Gain-Enhanced Active-Inductive CTLE and Reference-Selection DFE for Memory Interfaces. IEEE J. Solid State Circuits 59(4): 1261-1270 (2024) - [j9]Jincheol Sim, Changmin Sim, Hyunsu Park, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Jong-Min Kim, Ju-Hyung Lee, Young-Chai Ko, Chulwoo Kim:
A 10-Gb/s Wireline Receiver Using Linear Baud-Rate CDR and Analog Equalizer for Free Space Optical Communication Over 10- and 100-m Distances. IEEE J. Solid State Circuits 59(6): 1835-1846 (2024) - [j8]Jincheol Sim, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Hwaseok Shin, Junseob So, Seonbeen Lee, Chulwoo Kim:
A Wireline Transceiver With 3-bit per Symbol Using Common-Mode NRZ and Differential-Mode PAM-4 Signaling Techniques. IEEE J. Solid State Circuits 59(8): 2518-2528 (2024) - [j7]Seongcheol Kim, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Changmin Sim, Junseob So, Taehyeong Park, Chulwoo Kim:
Single-Ended PAM-4 Transmitters With Data Bus Inversion and ZQ Calibration for High-Speed Memory Interfaces. IEEE J. Solid State Circuits 59(10): 3432-3443 (2024) - [j6]Seongcheol Kim, Changmin Sim, Jincheol Sim, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Junseob So, Hwaseok Shin, Seonbeen Lee, Chulwoo Kim:
A 0.458-pJ/bit 24-Gb/s/pin Capacitively Driven PAM-4 Transceiver With PAM-Based Crosstalk Cancellation for High-Density Die-to-Die Interfaces. IEEE J. Solid State Circuits 59(11): 3730-3740 (2024) - [j5]Yoonjae Choi, Changmin Sim, Jonghyuck Choi, Jincheol Sim, Hyunsu Park, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Chulwoo Kim:
A 25-Gb/s Single-Ended PAM-4 Transmitter With iPWM-Based FFE and RLM-Matched Voltage-Mode Driver for High-Speed Memory Interfaces. IEEE Trans. Circuits Syst. I Regul. Pap. 71(12): 6375-6384 (2024) - [j4]Hyoshin Kang, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Chulwoo Kim:
A 13-Gb/s Single-Ended NRZ Receiver With 1-Sample Per 2-UI Using Data Edge Sampling for Memory Interfaces. IEEE Trans. Circuits Syst. II Express Briefs 71(7): 3328-3332 (2024) - [j3]Seungwoo Park, Yoonjae Choi, Jonghyuck Choi, Jincheol Sim, Youngwook Kwon, Changmin Sim, Seongcheol Kim, Chulwoo Kim:
A 0.45 pJ/b 24 Gb/s NRZ Receiver Data-Path Using Half-Baud-Rate Duobinary Sampling. IEEE Trans. Circuits Syst. II Express Briefs 71(9): 4096-4100 (2024) - 2023
- [j2]Yoonjae Choi, Hyunsu Park, Jonghyuck Choi, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Chulwoo Kim:
A 25-Gb/s Single-Ended PAM-4 Receiver With Time-Windowed LSB Decoder for High-Speed Memory Interfaces. IEEE J. Solid State Circuits 58(7): 2005-2015 (2023) - [j1]Yoonjae Choi, Hyunsu Park, Jonghyuck Choi, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Changmin Sim, Chulwoo Kim:
A 4-GHz Ring-Oscillator-Based Digital Sub-Sampling PLL With Energy-Efficient Dual-Domain Phase Detector. IEEE Trans. Circuits Syst. I Regul. Pap. 70(7): 2734-2743 (2023)
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