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ORCIDLucas Moura Santana
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2020 – today
- 2026
[c6]Ewout Martens, Angelo Parisi, Anirudh Kankuppe, Adam Cooman, Hanyue Li, Steven Van Winckel, Pratap Tumkur Renukaswamy, Lucas Moura Santana, Jorge Lagos, Nereo Markulic, Jan Craninckx:
11.5 A Compact 7b 175GS/s Linearized Time-Interleaved Slope ADC with Switched Input Buffers. ISSCC 2026: 198-200- 2023
- [c5]Lucas Moura Santana
, Ewout Martens, Jorge Lagos, Piet Wambacq, Jan Craninckx:
A 70MHz Bandwidth Time-Interleaved Noise-Shaping SAR Assisted Delta Sigma ADC with Digital Cross-Coupling in 28nm CMOS. ESSCIRC 2023: 389-392 - 2022
- [j1]Lucas Moura Santana, Ewout Martens, Jorge Lagos, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx:
A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS. IEEE J. Solid State Circuits 57(7): 2068-2077 (2022) - 2021
- [c4]Lucas Moura Santana, Ewout Martens, Jorge Lagos, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx:
A 47.5MHz BW 4.7mW 67dB SNDR Ringamp Based Discrete-Time Delta Sigma ADC. ESSCIRC 2021: 207-210
2010 – 2019
- 2018
- [c3]Higor A. Delsoto, Duarte Lopes de Oliveira, Lucas Moura Santana, Lester de Abreu Faria:
A design flow of asynchronous burst-mode circuits without fundamental-mode timing assumption. LASCAS 2018: 1-4 - [c2]Duarte Lopes de Oliveira, Tiago S. Curtinhas, Lucas Moura Santana, Lester de Abreu Faria:
A novel state assignment method for XBM AFSMs without the essential hazard assumption. LASCAS 2018: 1-4 - [c1]Duarte Lopes de Oliveira, Kledermon Garcia, Lucas Moura Santana, Lester de Abreu Faria:
FPGA implementation of high-performance asynchronous pipelines with robust control. LASCAS 2018: 1-4
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