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ORCIDJude Haris
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2020 – today
- 2026
[c4]Alain Pagani, José Cano, Haralampos-G. Stratigopoulos, Aysajan Abidin, Mhd Rashed Al Koutayni, Luca Benini, Angelos Bilas, Alessandro Capotondi, Roberto Cavicchioli, Brian Clerkin, Oscar Déniz-Suárez, Margaux Divernois, Baptiste Dupertuis, Dorvan Favre, Giulio Gambardella, Ander García Gangoiti, Carlo Augusto Grazia, Dominik Günzel, Jude Haris, Klodjan K. Hidri, Maïck Huguenin, Manal Jammal, Paul Kling, Christos Kozanitis, Xavier Lessage, Srikanth Mandapati, Philippe Massonet, Alfio Di Mauro, Varesh Mishra, Juan Odriozola, Javier Parra-Domínguez, Nuria Pazos, Viviane Potocnik, Miguel de Prado, Rohit Prasad, Spyridon Raptis, Gregoire Rebstein, Ignacio Sañudo Olmedo, Mohamed Selim, Chinmay Satish Shrivastav, Noelia Vállez, Giorgos Vasiliadis, Micaela Verrucchi, Enrico Vincenzi, Damian Vizár, Devendra Vyas, Stefan Wiehle:
Multi-Partner Project: dAIEDGE - A Network of Excellence for Distributed, Trustworthy, Efficient and Scalable AI at the Edge. DATE 2026: 1-7- [i11]Vinamra Sharma, Xingjian Fu, Jude Haris, José Cano:
LLM-Driven Design Space Exploration of FPGA-based Accelerators. CoRR abs/2605.05920 (2026) - [i10]Rappy Saha, Jude Haris, Nicolas Bohm Agostini, David R. Kaeli, José Cano:
PoTAcc: A Pipeline for End-to-End Acceleration of Power-of-Two Quantized DNNs. CoRR abs/2605.06082 (2026) - [i9]Vinamra Sharma, Xingjian Fu, Jude Haris, José Cano:
Towards Autonomous Accelerator Design: FPGA Accelerator Generation with SECDA. CoRR abs/2606.11117 (2026) - [i8]Elam Cohavi, Nicolas Bohm Agostini, Jude Haris, Antonino Tumeo, David R. Kaeli, José Cano:
Defeat the Heap: Zero-Copy Data Movement in AXI4MLIR. CoRR abs/2606.11158 (2026) - 2025
- [c3]Jude Haris, José Cano:
Accelerating Transposed Convolutions on FPGA-Based Edge Devices. FPL 2025: 305-313 - [i7]Jude Haris, José Cano:
Accelerating Transposed Convolutions on FPGA-based Edge Devices. CoRR abs/2507.07683 (2025) - [i6]Jude Haris, José Cano:
F-BFQ: Flexible Block Floating-Point Quantization Accelerator for LLMs. CoRR abs/2510.13401 (2025) - 2024
- [c2]Nicolas Bohm Agostini
, Jude Haris, Perry Gibson, Malith Jayaweera, Norm Rubin, Antonino Tumeo, José L. Abellán, José Cano, David R. Kaeli:
AXI4MLIR: User-Driven Automatic Host Code Generation for Custom AXI-Based Accelerators. CGO 2024: 143-157 - [i5]Jude Haris, Nicolas Bohm Agostini, Antonino Tumeo, David R. Kaeli, José Cano:
Data Transfer Optimizations for Host-CPU and Accelerators in AXI4MLIR. CoRR abs/2402.19184 (2024) - [i4]Jude Haris, Rappy Saha, Wenhao Hu, José Cano:
Designing Efficient LLM Accelerators for Edge Devices. CoRR abs/2408.00462 (2024) - [i3]Rappy Saha, Jude Haris, José Cano:
Accelerating PoT Quantization on Edge Devices. CoRR abs/2409.20403 (2024) - 2023
- [j1]Jude Haris, Perry Gibson, José Cano, Nicolas Bohm Agostini, David R. Kaeli:
SECDA-TFLite: A toolkit for efficient development of FPGA-based DNN accelerators for edge inference. J. Parallel Distributed Comput. 173: 140-151 (2023) - [i2]Nicolas Bohm Agostini, Jude Haris, Perry Gibson, Malith Jayaweera, Norm Rubin, Antonino Tumeo, José L. Abellán, José Cano, David R. Kaeli:
AXI4MLIR: User-Driven Automatic Host Code Generation for Custom AXI-Based Accelerators. CoRR abs/2312.14821 (2023) - 2021
- [c1]Jude Haris, Perry Gibson, José Cano, Nicolas Bohm Agostini, David R. Kaeli:
SECDA: Efficient Hardware/Software Co-Design of FPGA-based DNN Accelerators for Edge Inference. SBAC-PAD 2021: 33-43 - [i1]Jude Haris, Perry Gibson, José Cano, Nicolas Bohm Agostini, David R. Kaeli:
SECDA: Efficient Hardware/Software Co-Design of FPGA-based DNN Accelerators for Edge Inference. CoRR abs/2110.00478 (2021)
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