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Suresh Velliangiri

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2021
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Suresh Velliangiri, Senthilkumar Ramasamy, Prem Ponnusamy, M. Jagabar Sathik:
Design of nine step switched capacitor multilevel inverter and its cascaded extension. Int. J. Circuit Theory Appl. 49(4): 1182-1201 (2021)

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