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Youngjae Cho 0001
Person information
- affiliation: Samsung Electronics, Seoul, Korea
- affiliation (PhD 2007): Sogang University, Department of Electronic Engineering, Seoul, Korea
Other persons with the same name
- Youngjae Cho (aka: Young-Jae Cho) — disambiguation page
- Youngjae Cho 0002 — Korea Advanced Institute of Science and Technology (KAIST), Department of Industrial and Systems Engineering, Daejeon, Korea
- Youngjae Cho 0003 (aka: Young-Jae Cho 0003) — BMW Research and Technology, Munich, Germany
- Benjamin Y. Cho (aka: Benjamin Youngjae Cho, Youngjae Cho 0004) — University of Texas at Austin, TX, USA
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2020 – today
- 2026
[j10]Bo Gao
, Raymond Mabilangan
, Chang-Un Park
, Kent Edrian Lozada
, Ho-Jin Kim
, Youngjae Cho
, Michael Choi
, Seung-Tak Ryu
:
A 12-Bit 600-MS/s Pipelined ADC With Two-Stage High-Gain Dynamic Amplifier in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 73(4): 2371-2382 (2026)- 2025
[j9]Kent Edrian Lozada
, Ye-Dam Kim
, Ho-Jin Kim
, Youngjae Cho
, Michael Choi, Seung-Tak Ryu
:
A 0.38-mW 200-kHz-BW Digital-Intensive Single-Opamp Fourth-Order Continuous-Time Delta-Sigma Modulator With Third-Order Digital Noise Coupling in 28-nm CMOS. IEEE J. Solid State Circuits 60(4): 1236-1247 (2025)- 2024
[j8]Dong-Hun Lee
, Kent Edrian Lozada
, Ye-Dam Kim
, Ho-Jin Kim, Youngjae Cho
, Michael Choi, Seung-Tak Ryu
:
A 25-kHz-BW 97.4-dB-SNDR SAR-Assisted Continuous-Time 1-0 MASH Delta-Sigma Modulator With Digital Noise Coupling. IEEE J. Solid State Circuits 59(10): 3232-3241 (2024)
[j7]Jihun Choi
, Sangwook Na
, Hojin Kim, Hyungdong Roh, Youngjae Cho
, Michael Choi, Min-Seong Choo
, Jeongjin Roh
:
High-Precision Built-In Phase Noise Measurement Circuit With a Hybrid ΔΣ Time-to-Digital Converter for SoC Clocking Applications. IEEE Trans. Circuits Syst. II Express Briefs 71(11): 4613-4617 (2024)
[c16]Bo Gao
, Lizhen Zhang, Raymond Mabilangan, Chang-Un Park, Kent Edrian Lozada, Ho-Jin Kim, Youngjae Cho, Michael Choi, Seung-Tak Ryu:
A 28nm CMOS 12-bit-600-MS/s 15.6mW Pipelined ADC with Two-Stage Gainboosting FIA-based RA. A-SSCC 2024: 1-3
[c15]Sangheon Lee, Jinwoo Park, Junsang Park, Sangkyu Lee, Jungho Lee, Youngjae Cho
, Michael Choi, Jongshin Shin:
3.9 A 1.2V High-Voltage-Tolerant Bootstrapped Analog Sampler in 12-bit SAR ADC Using 3nm GAA's 0.7V Thin-Gate-Oxide Transistor. ISSCC 2024: 70-72
[c14]Byeongwoo Koo, Sunghan Do, Sangkyu Lee, Sang-Pil Nam, Heewook Shin, Saemin Im, Hyochul Shin, Sungno Lee, Junsang Park, Jungho Lee, Youngjae Cho
, Michael Choi, Jongshin Shin:
A 12-bit 16GS/s Single-Channel RF-DAC with Hybrid Segmentation for Digital Back-Off and Code-Dependent Free Switch Driver Achieving -85dBc IMD3 in 5nm FinFET. VLSI Technology and Circuits 2024: 1-2
[c13]Kent Edrian Lozada
, Ye-Dam Kim
, Ho-Jin Kim, Youngjae Cho
, Michael Choi, Seung-Tak Ryu:
A 0.38mW 200kHz-BW 92.1dB-DR Single-Opamp 4th-Order Continuous-Time Delta-Sigma Modulator with 3rd-Order Noise Coupling. VLSI Technology and Circuits 2024: 1-2
[c12]Junsang Park, Jinwoo Park, Jaemin Hong, Sun-Jae Park, Dongsuk Lee, Sungno Lee, Hyochul Shin, Kyung-Hoon Lee, Byeongwoo Koo, Youngjae Cho
, Michael Choi, Jongshin Shin:
A 12-bit 10GS/s Time-Interleaved SAR ADC with Even/Odd Channel-Correlated Absolute Error-Based Over-Nyquist Timing-Skew Calibration in 5nm FinFET. VLSI Technology and Circuits 2024: 1-2- 2023
[c11]Kent Edrian Lozada
, Dong-Hun Lee
, Ye-Dam Kim
, Ho-Jin Kim, Youngjae Cho
, Michael Choi, Seung-Tak Ryu:
A 25kHz-BW 97.4dB-SNDR 100.2dB-DR 3rd-Order SAR-Assisted CT DSM with 1-0 MASH and DNC. A-SSCC 2023: 1-3- 2022
[c10]Byeongwoo Koo, Sunghan Do, Sang-Pil Nam, Heewook Shin, Sungno Lee, Eunhye Oh, Jaemin Hong, Jung-Ho Lee, Youngjae Cho
, Michael Choi, Jongshin Shin:
A 12-bit 8GS/s RF Sampling DAC with Code-Dependent Nonlinearity Compensation and Intersegmental Current-Mismatch Calibration in 5nm FinFET. VLSI Technology and Circuits 2022: 86-87
[c9]Kyung-Hoon Lee, Jinwoo Park, Younghyo Park, Byeongwoo Koo, Sunghan Do, Woongtaek Lim, Sungno Lee, Hyochul Shin, Eunhye Oh, Youngjae Cho
, Michael Choi, Jongshin Shin:
An Automotive ASIL-D Safety Mechanism in ADC and DAC for Communication Application. VLSI Technology and Circuits 2022: 142-143
[c8]Kyoung-Jun Moon, Dong-Ryeol Oh
, Young-Hyo Park, Kyung-Hoon Lee, Sun-Jae Park, Sung-No Lee, Hee-Chang Hwang, Hyo-Chul Shin, Young-Jae Cho
, Michael Choi, Jongshin Shin:
A 12-bit 10GS/s 16-Channel Time-Interleaved ADC with a Digital Processing Timing-Skew Background Calibration in 5nm FinFET. VLSI Technology and Circuits 2022: 172-173- 2021
[c7]Seung-Yong Lim, Raymond Mabilangan, Dong-Jin Chang, Young-Jae Cho
, Michael Choi, Seung-Tak Ryu:
An Input-buffer Embedding Dual-residue Pipelined-SAR ADC with Nonbinary Capacitive Interpolation. A-SSCC 2021: 1-3
[c6]Seung-Yeob Baek, Il-Hoon Jang, Michael Choi, Hyungdong Roh, Woongtaek Lim, Youngjae Cho, Jongshin Shin:
A 12b 600MS/s Pipelined SAR and 2x-Interleaved Incremental Delta-Sigma ADC with Source-Follower-Based Residue-Transfer Scheme in 7nm FinFET. ISSCC 2021: 172-174
2000 – 2009
- 2007
[j6]Young-Ju Kim, Young-Jae Cho, Doo-Hwan Sa, Seung-Hoon Lee:
A 10 b 200 MS/s 1.8 mm2 83 mW 0.13µm CMOS ADC Based on Highly Linear Integrated Capacitors. IEICE Trans. Electron. 90-C(10): 2037-2043 (2007)- 2006
[j5]Byoung-Han Min, Young-Jae Cho, Hee-Sung Chae, Hee-Won Park, Seung-Hoon Lee:
A 10b 100 MS/s 1.4 mm256 mW 0.18 µm CMOS A/D Converter with 3-D Fully Symmetrical Capacitors. IEICE Trans. Electron. 89-C(5): 630-635 (2006)
[j4]Young-Jae Cho, Se-Won Kim, Kyung-Hoon Lee, Hee-Cheol Choi, Young-Lok Kim, Seung-Hoon Lee:
An Embedded 8b 240 MS/s 1.36 mm2 104 mW 0.18 µCMOS ADC for DVDs with Dual-Mode Inputs. IEICE Trans. Electron. 89-C(5): 636-641 (2006)
[c5]Young-Jae Cho
, Kyung-Hoon Lee, Hee-Cheol Choi, Young-Ju Kim, Kyoung-Jun Moon, Seung-Hoon Lee, Seok-Bong Hyun, Seong-Su Park:
A Dual-Channel 6b 1GS/s 0.18um CMOS ADC for Ultra Wide-Band Communication Systems. APCCAS 2006: 339-342
[c4]Kyung-Hoon Lee, Young-Jae Cho
, Hee-Cheol Choi, Yong-Hyun Park, Doo-Hwan Sa, Young-Lok Kim, Seung-Hoon Lee:
A 14b 100MS/s 3.4mm2 145mW 0.18um CMOS Pipeline A/D Converter. APCCAS 2006: 351-354
[c3]Young-Jae Cho
, Kyung-Hoon Lee, Hee-Cheol Choi, Seung-Hoon Lee, Kyoung-Ho Moon, Jae-Whui Kim:
A Calibration-Free 14b 70MS/s 3.3mm2 235mW 0.13um CMOS Pipeline ADC with High-Matching 3-D Symmetric Capacitors. CICC 2006: 485-488
[c2]Young-Jae Cho
, Doo-Hwan Sa, Yong-Woo Kim, Kyung-Hoon Lee, Hee-Cheol Choi, Seung-Hoon Lee, Young-Deuk Jeon, Seung-Chul Lee, Jong-Kee Kwon:
A 10b 25MS/s 4.8mW 0.13um CMOS ADC for Digital Multimedia Broadcasting Applications. CICC 2006: 497-500- 2005
[j3]Young-Jae Cho, Hyuen-Hee Bae, Seung-Hoon Lee:
An 8b 220 MS/s 0.25 µm CMOS Pipeline ADC with On-Chip RC-Filter Based Voltage References. IEICE Trans. Electron. 88-C(4): 768-772 (2005)
[j2]Young-Jae Cho
, Seung-Hoon Lee:
An 11b 70-MHz 1.2-mm2 49-mW 0.18-μm CMOS ADC with on-chip current/voltage references. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(10): 1989-1995 (2005)
[c1]Se-Won Kim, Young-Jae Cho
, Kyung-Hoon Lee, Seung-Hoon Lee, Jae-Yup Lee, Hyun-Chul Noh, Hee-Sub Lee:
An 8b 240 MS/s 1.36 mm2 104 mW 0.18 um CMOS ADC for DVDs with dual-mode inputs. ISCAS (4) 2005: 4054-4057- 2004
[j1]Jong-Bum Park
, Sang-Min Yoo, Se-Won Kim, Young-Jae Cho
, Seung-Hoon Lee:
A 10-b 150-MSample/s 1.8-V 123-mW CMOS A/D converter with 400-MHz input bandwidth. IEEE J. Solid State Circuits 39(8): 1335-1337 (2004)
Coauthor Index

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last updated on 2026-04-25 00:43 CEST by the dblp team
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