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ORCIDYuekang Guo
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- affiliation: Shanghai Jiao Tong University, China
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2020 – today
- 2026
[j18]Yuxiang Li, Jing Jin
, Yuekang Guo, Jianjun Zhou, Junmin Jiang:
A 3-5 V to Sub-1 V DLDO-SC-Sigma Converter With Auxiliary Loop for Efficiency Improvement in High-Density Power Delivery. IEEE J. Solid State Circuits 61(2): 641-650 (2026)- [j17]Huzhi Tang, Yuekang Guo, Jing Jin, Xiaoming Liu, Yi Liu, Zhongyuan Chang, Howard C. Yang, Jianjun Zhou:
A 40-nm CMOS Phase-Tunable Four-Phase Injection-Locked Ring VCO Utilizing Unbalanced Feedforward Topology Achieving -211.1- to -207.3-dBc/Hz FoMA Over Differential/Orthogonal Phase Range of -90.0° to 80.9°/-69.6° to 76.5°. IEEE J. Solid State Circuits 61(5): 2004-2018 (2026) - [j16]Qiang Pan, Yitao Wang, Jiayi Chen, Yuekang Guo, Jing Jin, Jianjun Zhou:
A 14-bit 1.4 GS/s current-steering DAC with square-dithered frequency-modulated DEM achieving >60-dBc SFDR in 180 nm CMOS. Microelectron. J. 167: 106953 (2026) - [j15]Qiang Pan, Yuekang Guo, Chao Yang, Jing Jin, Jianjun Zhou:
An energy-efficient 128 Gb/s PAM-4 wireline transmitter with a passive 4:1 MUX in 22 nm CMOS. Microelectron. J. 175: 107287 (2026) - [c18]Zizhe Huang, Yuxiang Li, Yuekang Guo, Jing Jin, Jianjun Zhou, Junmin Jiang:
A 5-to-1V DLDO-Hybrid-Sigma Converter Achieving Fast Transient for High-Density Power Delivery. ASP-DAC 2026: 216-218 - 2025
- [j14]Tao Zhong, Yuekang Guo, Jing Jin, Jianjun Zhou:
A two-phase oscillation scheme with direct background correction for VCO-based ADC. Microelectron. J. 159: 106644 (2025) - [j13]Hui Zhang, Dawei Dong, Haijun Wang, Dan Li, Yuan Gao, Chaoyi Hu, Hao Xu, Xinlei Song, Jing Jin, Yuekang Guo, Lin Cheng:
A 14-bit 2.6GS/s RF sampling pipelined ADC in 28nm CMOS. Microelectron. J. 164: 106795 (2025) - [j12]Hui Zhang, Yong Li, Dawei Dong, Danben He, Yuan Gao, Jing Jin, Yuekang Guo, Lei Qiu, Zhenrong Li, Lin Cheng:
A 78.1 dB SNDR 10 MHz-BW continuous-time noise-shaping SAR ADC in 28 nm CMOS. Microelectron. J. 165: 106839 (2025) - [j11]Tao Zhong, Yuekang Guo, Jianjun Zhou, Hui Zhang, Jing Jin:
A 25 MHz-BW 81 dB-DR TDC-Based CTDSM With Background Analog-Integration-Based ISI Error Calibration Achieving >8 dB Even-Order Harmonic Suppression. IEEE Trans. Circuits Syst. I Regul. Pap. 72(11): 6701-6712 (2025) - [j10]Ke Wu, Yuekang Guo, Xiaoming Liu, Zhongyuan Chang, Howard C. Yang, Jing Jin, Jianjun Zhou:
A Fully Symmetric Oscillator-Based CMOS Ising Machine Architecture With Successive Approximation Sampling and Power Efficient Solution Refinement. IEEE Trans. Circuits Syst. I Regul. Pap. 72(11): 6713-6723 (2025) - [j9]Jing Jin, Meng Xu, Yuekang Guo, Xiaoming Liu, Nan Sun, Jianjun Zhou:
A 470 μW 20 kHz-BW 107.3 dB-SNDR Nested CT DSM Using Negative-R-Based Cross-RC Integrator and Weighted Multi-Threshold MSB-Pass Quantizer. IEEE Trans. Circuits Syst. I Regul. Pap. 72(11): 6807-6819 (2025) - [c17]Yuzhi Ai, Yuekang Guo, Zhengyuan Lou, Hui Zhang, Jing Jin, Jianjun Zhou:
An EF-CIFF Noise-Shaping SAR ADC with A Joint Dynamic Amplifier, Comparator and Lossless Passive Summer Structure. ISCAS 2025: 1-5 - [c16]Jinwei Wu, Yuekang Guo, Meng Xu, Lingyan Fan, Jing Jin, Jianjun Zhou:
A1-GS/s 7-bit 3-then-1 bit/cycle SAR ADC with A Reconfigurable Reference-Embedded Comparator. ISCAS 2025: 1-5 - 2024
- [j8]Xiaofei Wang, Jing Jin, Xiaoming Liu, Hui Wang, Huzhi Tang, Chao Yang, Yuekang Guo, Tingting Mo, Jianjun Zhou:
A 0.83-pJ/b 20-Gb/s/Pin Single-Ended Transceiver With AC/DC-Coupled Pre-Emphasis FFE and Edge-Dependent Phase-Modulation DFE for Low-Power Memory Controllers. IEEE Trans. Circuits Syst. I Regul. Pap. 71(2): 560-572 (2024) - [c15]Jing Jin, Yuekang Guo, Meng Xu, Xiaoming Liu, Nan Sun, Jianjun Zhou:
A 470μW 20kHz-BW 107.3dB-SNDR Nested CT DSM Employing Negative-R-Based Cross-RC Filter and Weighted Multi-Threshold MSB-Pass Quantizer. CICC 2024: 1-2 - [c14]Zhengyuan Lou, Meng Xu, Yuekang Guo, Jing Jin, Jianjun Zhou:
A Self-Calibrated Sampling Noise Cancellation Technique for Noise-Shaping SAR ADC. ISCAS 2024: 1-5 - 2023
- [j7]Yuekang Guo, Jing Jin, Xiaoming Liu, Jianjun Zhou:
A 60-MS/s 5-MHz BW Noise-Shaping SAR ADC With Integrated Input Buffer Achieving 84.2-dB SNDR and 97.3-dB SFDR Using Dynamic Level-Shifting and ISI-Error Correction. IEEE J. Solid State Circuits 58(2): 474-485 (2023) - [j6]Yuekang Guo, Jing Jin, Xiaoming Liu, Jianjun Zhou:
A 372 μW 10 kHz-BW 109.2 dB-SNDR Nested Delta-Sigma Modulator Using Hysteresis-Comparison MSB-Pass Quantization. IEEE J. Solid State Circuits 58(9): 2554-2563 (2023) - [c13]Yuekang Guo, Jing Jin, Xiaoming Liu, Zhaolin Yang, Jianjun Zhou:
A LUT-based Background Linearization Technique for VCO-based ADC Employing $K_{\text{VCO}}-\text{Locked}-\text{Loop}$. ISCAS 2023: 1-4 - [c12]Shunyan Wang, Yuekang Guo, Qiang Pan, Xiaoming Liu, Shan Wang, Jing Jin:
A Fully Synthesizable Dynamic Voltage Comparator with Time-Domain Offset Calibration. MWSCAS 2023: 482-485 - [c11]Ke Wu, Yuekang Guo, Xiaoming Liu, Jing Jin, Howard C. Yang, Jianjun Zhou:
A Non-Linearity Digital Background Calibration Algorithm with Piece-Wise Linear Functions. MWSCAS 2023: 609-613 - 2022
- [j5]Ran Bu, Jing Jin, Zhaolin Yang, Yuekang Guo, Jianjun Zhou:
A Harmonic Rejecting N-Path Filter with Harmonic Gain Calibration Technique. Circuits Syst. Signal Process. 41(12): 6672-6693 (2022) - [j4]Yuekang Guo, Jing Jin, Xiaoming Liu, Jianjun Zhou:
An 18.1 mW 50 MHz-BW 76.4 dB-SNDR CTSDM With PVT-Robust VCO Quantizer and Latency-Free Background-Calibrated DAC. IEEE Trans. Circuits Syst. I Regul. Pap. 69(12): 4787-4798 (2022) - [j3]Chao Yang, Xiaoming Liu, Jing Jin, Yuekang Guo, Jianjun Zhou:
A Fast-Settling Phase-Locked Loop Utilizing Cycle-Slipping-Elimination PFDCP. IEEE Trans. Circuits Syst. II Express Briefs 69(10): 3998-4002 (2022) - [c10]Yuekang Guo, Xiaoming Liu, Jing Jin, Jianjun Zhou:
A 3bit/cycle 1GS/s 8-bit SAR ADC Employing Asynchronous Ping-Pong Quantization Scheme. ISCAS 2022: 2650-2654 - [c9]Ke Wu, Yuekang Guo, Jing Jin, Xiaoming Liu, Jianjun Zhou:
A Power-Efficient CMOS Image Sensor with In-Sensor Processing and In-Pixel Gain Calibration. MWSCAS 2022: 1-4 - 2021
- [j2]Mengying Hu, Jing Jin, Yuekang Guo, Xiaoming Liu, Jianjun Zhou:
A Power-Efficient SAR ADC with Optimized Timing-Redistribution Asynchronous SAR Logic in 40-nm CMOS. Circuits Syst. Signal Process. 40(7): 3125-3142 (2021) - [c8]Tao Zhong, Yuekang Guo, Jing Jin:
Analysis of SAR ADC Quantization Error and Nonlinearity in PMCW Automotive Radar. ASICON 2021: 1-4 - [c7]Yuekang Guo, Jing Jin, Xiaoming Liu, Jianjun Zhou:
A Phase Domain Excess Loop Delay Compensation Technique with Latency Optimized Phase Selector for VCO-Based Continuous-Time ΔΣ ADC. ISCAS 2021: 1-4 - [c6]Yuekang Guo, Jing Jin, Jianjun Zhou:
A Low Power PVT Stabilization Technique for Dynamic Amplifier in Pipelined SAR ADC. MWSCAS 2021: 18-21 - [c5]Yuekang Guo, Qiang Pan, Xiaoming Liu, Jing Jin:
A Center Frequency Calibration Technique for Ring VCO Exploiting Delay-1 Detection. MWSCAS 2021: 708-711 - [c4]Qiang Pan, Yuekang Guo, Jing Jin, Jianjun Zhou:
A Linearization Technique for Ring VCO Exploiting Bulk-Modulation. MWSCAS 2021: 737-740 - [c3]Yanlin He, Yuekang Guo, Jing Jin, Jianjun Zhou:
A Latency-Optimized Lookup Table for Nonlinearity Calibration in VCO-Based Sigma-Delta ADCs. MWSCAS 2021: 941-944 - 2020
- [j1]Yuekang Guo, Jing Jin, Xiaoming Liu, Jianjun Zhou:
An Inverter-Based Continuous Time Sigma Delta ADC With Latency-Free DAC Calibration. IEEE Trans. Circuits Syst. 67-I(11): 3630-3642 (2020) - [c2]Ran Wang, Yuekang Guo, Jing Jin, Xiaoming Liu, Naifeng Jing, Jianjun Zhou:
A Low Power Temperature-Compensated Common-Mode Voltage Detector for Dynamic Amplifiers. ISCAS 2020: 1-4
2010 – 2019
- 2019
- [c1]Yifei Wang, Xiaofei Wang, Yuekang Guo, Ting Jin:
A Low-Power 10-bit 160-MSample/s DAC in 40-nm CMOS for Baseband Wireless Transmitter. ASICON 2019: 1-4
Coauthor Index
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