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Imad Benacer

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

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2020 – today

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2025
[c7]
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Fateh Moulahcene, Rostom Khalef, Ammar Merazga, Imad Benacer, Salah Hanfoug, Hichem Laib:
Low-cost Arduino-Based Implementation of PWM Boost Converter for PV Systems. ICECET 2025: 1-6

2010 – 2019

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2019
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Imad Benacer, François-Raymond Boyer, Yvon Savaria:
A High-Speed, Scalable, and Programmable Traffic Manager Architecture for Flow-Based Networking. IEEE Access 7: 2231-2243 (2019)
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Imad Benacer, François-Raymond Boyer, Yvon Savaria:
HPQS: A Fast, High-Capacity, Hybrid Priority Queuing System for High-Speed Networking Devices. IEEE Access 7: 130672-130684 (2019)
2018
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Imad Benacer, François-Raymond Boyer, Yvon Savaria:
A Fast, Single-Instruction-Multiple-Data, Scalable Priority Queue. IEEE Trans. Very Large Scale Integr. Syst. 26(10): 1939-1952 (2018)
[c6]
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Imad Benacer, François-Raymond Boyer, Yvon Savaria:
Design of a Low Latency 40 Gb/s Flow-Based Traffic Manager Using High-Level Synthesis. ISCAS 2018: 1-5
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Imad Benacer, François-Raymond Boyer, Yvon Savaria:
HPQ: A High Capacity Hybrid Priority Queue Architecture for High-Speed Network Switches. NEWCAS 2018: 229-233
2017
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Imad Benacer, François-Raymond Boyer, Yvon Savaria:
A high-speed traffic manager architecture for flow-based networking. NEWCAS 2017: 161-164
2016
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Imad Benacer, Zohir Dibi:
Extracting parameters of OFET before and after threshold voltage using genetic algorithms. Int. J. Autom. Comput. 13(4): 382-391 (2016)
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Imad Benacer, François-Raymond Boyer, Normand Bélanger, Yvon Savaria:
A fast systolic priority queue architecture for a flow-based Traffic Manager. NEWCAS 2016: 1-4
2015
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Imad Benacer, Aicha Hamissi, Abdelhakim Khouas:
A novel stereovision algorithm for obstacles detection based on U-V-disparity approach. ISCAS 2015: 369-372
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Imad Benacer, Aicha Hamissi, Abdelhakim Khouas:
Hardware design and FPGA implementation for road plane extraction based on V-disparity approach. ISCAS 2015: 2053-2056

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