Design of high-linearity delay detection circuit for 10-Gb/s communication system in 65-nm CMOS.

Fri, 01 Jan 2016 00:00:00 +0100

Kosuke Furuichi, Hiromu Uemura, Natsuyuki Koda, Hiromi Inaba, Keiji Kishine:
Design of high-linearity delay detection circuit for 10-Gb/s communication system in 65-nm CMOS. ISOCC 2016: 261-262