Design method for an over-IO-Gb/s CMOS CML buffer circuit for delay control.

Sun, 01 Jan 2012 00:00:00 +0100

Keiji Kishine, Hiromi Inaba, Yusuke Ohtomo, Makoto Nakamura, Mitsuo Nakamura:
Design method for an over-IO-Gb/s CMOS CML buffer circuit for delay control. MWSCAS 2012: 602-605