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ORCIDHarijot Singh Bindra
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2020 – today
- 2026
[j9]Jeroen Ponte
, Roel Plompen, Emiel Zijlma, Eric A. M. Klumperink, Harijot Singh Bindra, Bram Nauta:
A "No Gain" Direct-Conversion IQ RF-to-Bits Receiver Without Active Linear Amplification. IEEE J. Solid State Circuits 61(6): 2614-2630 (2026)- [j8]Anojh Kumaran Rajendra, Harijot Singh Bindra, Bram Nauta:
Ultra-Low-Power Dynamic-Bias Comparators With Self-Clocked Latch in 65-nm CMOS. IEEE J. Solid State Circuits 61(6): 2821-2833 (2026) - 2025
- [j7]Viswesh Kendae Ramkumar, Maikel Huiskamp, Harijot Singh Bindra, Eric A. M. Klumperink, Bram Nauta:
A Programmable Filtering and Frequency Translation by Aliasing IF Receiver With Alias and Harmonic Rejection. IEEE J. Solid State Circuits 60(6): 1997-2012 (2025) - [j6]Josef Heel, Harijot Singh Bindra, Simon M. Louwsma, Alessandro Dezzani, Bram Nauta:
A 12.8-GS/s Time-Interleaved Sub-Sampling ADC Front End With 38-GHz Input Bandwidth and >39-dB SNDR for 1-32 GHz in 22-nm FDSOI. IEEE J. Solid State Circuits 60(12): 4321-4335 (2025) - [j5]Jeroen Ponte, Harijot Singh Bindra, Bram Nauta:
A 0.4-0.9 V Supply Voltage-Flexible Third-Order Passive ΔΣ Modulator With Switched-Capacitor Loop Filter Achieving 71.9 dB Peak SNDR at 4 MHz Bandwidth. IEEE Trans. Circuits Syst. I Regul. Pap. 72(10): 5365-5377 (2025) - [c10]Viswesh Kendae Ramkumar, Harijot Singh Bindra, Eric A. M. Klumperink, Basem Abdelaziz Abdelmagid, Hua Wang:
Time Modulated Array and Time Variant Filter Techniques to Reduce Receiver Hardware Complexity and Power Consumption. EuCNC/6G Summit 2025: 1-6 - [c9]Anojh Kumaran Rajendra, Jordi Freriksen, Harijot Singh Bindra:
Dynamic-Window DAC Switching in SAR ADCs and its Mismatch Modelling for High Peak-to-Average Ratio Input Signals. ISCAS 2025: 1-5 - [c8]Josef Heel, Harijot Singh Bindra, Simon M. Louwsma, Alessandro Dezzani, Bram Nauta:
A 12.8GS/s Sub-Sampling ADC Front-End With 38GHz Input Bandwidth and >39dB SNDR for 1 to 32GHz in 22nm FDSOI. ISSCC 2025: 76-78 - 2023
- [j4]Yuting Shen, Hanyue Li, Harijot Singh Bindra, Eugenio Cantatore, Pieter Harpe:
A 14-Bit Oversampled SAR ADC With Mismatch Error Shaping and Analog Range Compensation. IEEE Trans. Circuits Syst. II Express Briefs 70(5): 1719-1723 (2023) - 2022
- [j3]Maikel Huiskamp, Mark S. Oude Alink, Bram Nauta, Anne-Johan Annema, Harijot Singh Bindra:
Reconstructing Aliased Frequency Spectra by Using Multiple Sample Rates. IEEE Trans. Circuits Syst. I Regul. Pap. 69(3): 999-1012 (2022) - [c7]Harijot Singh Bindra, Jeroen Ponte, Bram Nauta:
A 174μVRMS Input Noise, 1 G8/s Comparator in 22nm FDSOI with a Dynamic-Bias Preamplifier Using Tail Charge Pump and Capacitive Neutralization Across the Latch. ISSCC 2022: 1-3 - 2021
- [j2]Joeri Lechevallier, Harijot Singh Bindra, Ronan A. R. van der Zee, Bram Nauta:
Energy Efficient Startup of Crystal Oscillators Using Stepwise Charging. IEEE J. Solid State Circuits 56(8): 2427-2437 (2021)
2010 – 2019
- 2019
- [c6]Harijot Singh Bindra, Anne-Johan Annema, Gerard Wienk, Bram Nauta, Simon M. Louwsma:
A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply. CICC 2019: 1-4 - [c5]Harijot Singh Bindra, Anne-Johan Annema, Simon M. Louwsma, Bram Nauta:
A 0.2 - 8 MS/s 10b flexible SAR ADC achieving 0.35 - 2.5 fJ/conv-step and using self-quenched dynamic bias comparator. VLSI Circuits 2019: 74- - 2018
- [j1]Harijot Singh Bindra, Chris E. Lokin, Daniël Schinkel, Anne-Johan Annema, Bram Nauta:
A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise. IEEE J. Solid State Circuits 53(7): 1902-1912 (2018) - 2017
- [c4]Harijot Singh Bindra, Joeri Lechevallier, Anne-Johan Annema, Simon M. Louwsma, Ed van Tuijl, Bram Nauta:
Range pre-selection sampling technique to reduce input drive energy for SAR ADCs. A-SSCC 2017: 217-220 - [c3]Harijot Singh Bindra, Chris E. Lokin, Anne-Johan Annema, Bram Nauta:
A 30fJ/comparison dynamic bias comparator. ESSCIRC 2017: 71-74 - [c2]Harijot Singh Bindra, Anne-Johan Annema, Simon M. Louwsma, Ed J. M. van Tuijl, Bram Nauta:
An energy reduced sampling technique applied to a 10b 1MS/s SAR ADC. ESSCIRC 2017: 235-238 - 2013
- [c1]Harijot Singh Bindra, Shouri Chatterjee, Kaushik Saha, Taranjit Kukal:
Clock and data recovery module in 90nm for 10Gbps serial link with -18dB channel attenuation. ISCAS 2013: 2472-2475
Coauthor Index
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