default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDMicroprocessors and Microsystems, Volume 27
Volume 27, Number 1, February 2003
- Luciano Boquete, Ignacio Bravo Muñoz
, Rafael Barea, Miguel Ángel García:
Telemetry and control system with GSM communications. 1-8 - Abdulhussain E. Mahdi, Ian Andrew Grout:
PLL based ASIC system for DSP real-time analogue interface. 9-17 - Jochen Kreuzinger, Uwe Brinkschulte, Matthias Pfeffer, Sascha Uhrig, Theo Ungerer:
Real-time event-handling and scheduling on a multithreaded Java microcontroller. 19-31 - Alfredo Rosado, Manuel Bataller-Mompeán, Juan Guerrero-Martínez, Javier Calpe, José V. Francés, José Rafael Magdalena Benedicto:
High performance hardware correlation coefficient assessment using programmable logic for ECG signals. 33-39
Volume 27, Number 2, March 2003
- Paolo Bellavista:
Middleware solutions for QoS in distributed multimedia services. 43-44 - Nanbor Wang, Douglas C. Schmidt, Aniruddha S. Gokhale, Christopher D. Gill, Balachandran Natarajan, Craig Rodrigues, Joseph P. Loyall, Richard E. Schantz:
Total quality of service provisioning in middleware and applications. 45-54 - Domenico Cotroneo, Giulio Iannello, Stefano Russo, Giorgio Ventre:
A real time-based architecture for qos multimedia provisioning. 55-63 - Won Jong Jeon, Klara Nahrstedt:
QoS-aware middleware support for collaborative multimedia streaming and caching service. 65-72 - Paolo Bellavista, Antonio Corradi:
Active middleware for Internet Video on Demand: the QoS-aware routing solution in ubiQoS. 73-83 - Dario Bruneo, Massimo Villari, Angelo Zaia, Antonio Puliafito:
QoS management for MPEG-4 flows in wireless environment. 85-92 - Bob Askwith, Madjid Merabti, Qi Shi:
MNPA: A basis for privacy-enhanced QoS in mobile networks. 93-100
Volume 27, Number 3, April 2003
- Ahmed Yassin Al-Dubai, Mohamed Ould-Khaoua:
A new scalable broadcast algorithm for multiport meshes with minimum communication steps. 101-113 - Camel Tanougast, Yves Berviller, Philippe Brunet, Serge Weber, Hassan Rabah:
Temporal partitioning methodology optimizing FPGA resources for dynamically reconfigurable embedded real-time system. 115-130 - Wael M. Badawy:
A VLSI architecture for video object motion estimation using a 2D hierarchical mesh model. 131-140 - Bhooshan S. Thakar, Sun Kyu Park, Gyungho Lee:
A scalable multi-porting solution for future wide-issue processors. 141-149
Volume 27, Number 4, May 2003
- Hee-Sub Lee, Jae Wook Jeon, Joon-Woo Kim, Sung-Jong Jung, Jong-Eun Byun:
A 12-inch wafer prealigner. 151-158 - Iain Bate, John A. McDermid, Peter Nightingale:
Establishing timing requirements for control loops in real-time systems. 159-169 - Cheol-Ho Jeong, Woo-Chan Park, Tack-Don Han, Sung-Bong Yang, Moon-Key Lee:
An effective out-of-order execution control scheme for an embedded floating point coprocessor. 171-180 - Borislav S. Djordjevic, Stanislav M. Miskovic:
Disk interface comparison and operating system file-caching investigation. 181-198 - Sotirios G. Ziavras:
Processor design based on dataflow concurrency. 199-220 - K. Rajan, Lalit M. Patnaik:
Implementation of STAP algorithms on IBM SP2 and on ADSP 21062 dual digital signal processor systems. 221-227
Volume 27, Numbers 5-6, June 2003
- Arun K. Somani:
Advances in computer communication networks and applications. 229-231 - Ferdinand Gramsamer, Mitchell Gusat, Ronald P. Luijten:
Flow control scheduling. 233-241 - Mitchell Gusat, François Abel, Ferdinand Gramsamer, Ronald P. Luijten, Cyriel Minkenberg, Mark Verhappen:
Stability degree of switches with finite buffers and non-negligible round-trip time. 243-252 - Mehrdad Nourani, Mohammad J. Akhbarizadeh:
Reconfigurable memory architecture for scalable IP forwarding engines. 253-263 - Sungwoo Tak, Yugyung Lee, Eun Kyo Park:
A software framework for non-repudiation service in electronic commerce based on the Internet. 265-276 - Ka Lun Eddie Law, Roy Leung:
A design and implementation of active network socket programming. 277-284 - Sonal Pandey, Arun K. Somani, Akhilesh Tyagi:
Intermediate processing protocol for processing within IP-routed networks. 285-295
Volume 27, Number 7, August 2003
- Yeong-Gang Show, Yi-Chia Chang, Qi-Nan Liao, Kou-Tan Wu:
Design of SDH STM-1 transmission test set. 297-302 - Gholamreza Latif Shabgahi, Stuart Bennett, Julian M. Bass:
Smoothing voter: a novel voting algorithm for handling multiple errors in fault-tolerant control systems. 303-313 - Yeong-Gang Show, Yi-Chia Chang, Kou-Tan Wu:
Asymmetric digital subscriber line access multiplexer - architecture design and implementation. 315-326 - George Hassapis:
Implementation of model predictive control using real-time multiprocessing computing. 327-340 - Alfred Strey:
On the suitability of SIMD extensions for neural network simulation. 341-351
Volume 27, Number 8, September 2003
- José F. Toledo Alarcón, Francisco J. Mora, Hans Müller:
Past, present and future of data acquisition systems in high energy physics experiments. 353-358 - Ming-Jung Seow, Hau T. Ngo, Vijayan K. Asari:
Systolic implementation of 2D block-based Hopfield neural network for efficient pattern association. 359-366 - Gary Jones, Elias Stipidis:
Architecture and instruction set design of an ATM network processor. 367-379 - Georgios Ch. Sirakoulis, Ioannis Karafyllidis, Adonios Thanailakis:
A CAD system for the construction and VLSI implementation of Cellular Automata algorithms using VHDL. 381-396 - Álvaro Hernández, Jesús Ureña, Daniel Hernanz, Juan Jesús García, Manuel Mazo, Jean-Pierre Dérutin, Jocelyn Sérot, Sira E. Palazuelos:
Real-time implementation of an efficient Golay correlator (EGC) applied to ultrasonic sensorial systems. 397-406
Volume 27, Number 9, October 2003
- Steve B. Furber:
Editorial. 407-408 - Brian D. Winters, Mark R. Greenstreet:
Surfing: a robust form of wave pipelining using self-timed circuit techniques. 409-419 - Simon W. Moore, Ross J. Anderson, Robert Mullins, George S. Taylor, Jacques J. A. Fournier:
Balanced self-checking asynchronous logic for smart card applications. 421-430 - Luis A. Plana, Peter A. Riocreux, W. J. Bainbridge, Andrew Bardsley, Steve Temple, Jim D. Garside, Z. C. Yu:
SPA - a secure Amulet core for smartcard applications. 431-446 - Joep L. W. Kessels, Ad M. G. Peeters, Paul Wielage, Suk-Jin Kim:
Clock synchronization through handshake signalling. 447-460 - Kees van Berkel, Ad M. G. Peeters, Frank te Beest:
Adding synchronous and LSSD modes to asynchronous circuits. 461-471 - D. J. Kinniment, Oleh V. Maevsky, Alexandre V. Bystrov, Gordon Russell, Alexandre Yakovlev:
On-chip structures for timing measurement and test. 473-483
Volume 27, Number 10, November 2003
- Daranee Hormdee, Jim D. Garside, Stephen B. Furber:
An asynchronous copy-back cache architecture. 485-500 - R. Subramaniam, R. Sharadh, K. M. M. Prabhu:
Performance of dual tone multi-frequency signal decoding algorithm using the sub-band non-uniform discrete Fourier transform on the ADSP-2192 processor. 501-510 - V. Ashok Narayanan, K. M. M. Prabhu:
The fractional Fourier transform: theory, implementation and error analysis. 511-521 - Nam Hee Lee, Sung Deok Cha:
Generating test sequences using symbolic execution for event-driven real-time systems. 523-531
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2026-08-12 22:58 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated, funded, and maintained by:
Schloss Dagstuhl - Leibniz Center for Informatics is a member of the Leibniz Association and is funded by the federal government of Germany and the states of Germany, especially Saarland and Rhineland‑Palatinate.
