default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDMicroprocessors and Microsystems, Volume 18
Volume 18, Number 1, January - February 1994
- M. J. P. Bolton:
Editorial. 3-4 - George Kechriotis, Elias S. Manolakos
:
Training fully recurrent neural networks on a ring transputer array. 5-11 - Nick Tsakalos, Evangelos Zigouris:
Use of a single chip fixed-point DSP for multiple speech channel vocoders. 12-18 - T. Hanif, Mark B. Sandler:
A counter-based Hough transform system. 19-26 - Phil A. Witting:
A technique for the implementation of low frequency digital filters with simple FAD-based hardware. 27-38 - Meng Hwa Er, T. H. Ooi, L. S. Li, C. J. Liew:
A DSP-based acoustic feedback canceller for public address systems. 39-47 - Yong-In S. Shin:
Live insertion considerations for Philips TTL bus-interface logic devices. 48-51 - Jim E. Cooling:
Object-Oriented Interfacing to 16-bit Microcontrollers: G J Lipovski Prentice Hall, Hemel Hempstead, UK (1993) ISBN 0 13 629221 6, £33.95, pp 490. 52 - Chris R. Jesshope:
Mechanized Reasoning and Hardware Design: C A R Hoare and M J C Gordon (Eds) Prentice Hall, Hemel Hempstead, UK (1992) ISBN 0 13 572405 8, £40, pp 151. 53 - Bill Postlethwaite:
Assembly Language and Systems Programming for the M68000 Family (second edition): William Ford and William Topp D. C. Heath, Toronto, Canada (1992) ISBN 0 669 28199 9, $44 (UK £22.95 for educational establishments) pp 890 + 240 appendix. 54 - Simon Jones:
Digital BiCMOS Integrated Circuit Design: Sherif H K Embabi, A. Bellaouar and Mohamed I Elmasry Kluwer Academic, Dordrecht, The Netherlands (1992) ISBN 0 7923 9276 0, £62.50, pp 432. 55
Volume 18, Number 2, March 1994
- J. N. H. Heemskerk, Jaap Hoekstra, Jacob M. J. Murre, Leon H. J. G. Kemna, Patrick T. W. Hudson:
The BSP400: a modular neurocomputer. 67-78 - Wei-Jou Duh, Ja-Ling Wu, Jau-Hsiung Huang:
A multiprocessor system for visual communications using distributed transputer arrays. 79-87 - Anthony S. White, C. Kelly:
Optimization of a control algorithm using a simulation package. 89-94 - Ivor T. A. Spence:
Displaying digital images in a distributed processing environment. 95-99 - K. V. M. Deva Raju, S. V. Subba Rao, K. V. Srinivasan, K. Visvanathan:
Multichannel real-time data acquisition system using dual ported FIFO buffers. 101-108 - David Wilson:
16-bit DSP servo control with the MC68HC16Z1. 109-117
Volume 18, Number 3, April 1994
- Padmanabhan Krishnan:
A case study in specifying and testing architectural features. 123-130 - John Lenell, Nader Bagherzadeh:
A performance comparison of several superscalar processor models with a VLIW processor. 131-139 - K. Vijayakumar, Vinod S. S. Chandra:
Transputer-based fault-tolerant and fail-safe node for dual ring distributed railway signalling systems. 141-150 - A. M. Mukherjee, Andrew M. Tyrrell:
Investigating the effects of induced faults in transputer systems. 151-163 - Brian R. Kirk:
Designing systems with objects, processes and modules. 165-171 - Tarlton Fleming:
3 V systems spur evolution of the RS-232 standard. 173-177 - Roger M. A. Peel:
Transputer Hardware and System Design : Jeremy Hinton and Alan Pinder Prentice Hall International, Hemel Hempstead, UK (1993) ISBN 0 13 953001 0, £19.95. pp 286. 179 - Ferenc Vajda:
Nineteenth Euromicro Conference : Barcelona, Spain, 6-9 September 1993. 180-181
Volume 18, Number 4, May 1994
- A. Sreenivas, K. N. Balasubramanya Murthy, C. Siva Ram Murthy:
Reverse scheduling - an effective method for scheduling tasks of parallel programs employing a divide-and-conquer strategy onto multiprocessors. 187-192 - Gul N. Khan, Khalid Mahmud, M. Salman Igbal, Haroon-Ur-Rashid Khan:
RSM - a restricted shared memory architecture for high speed interprocessor communication. 193-203 - A. A. Wardak, G. A. King, R. Backhouse:
Interfacing high-level and assembly language with microcodes in 3-D image generation. 205-213 - Chris Swan, David M. Howard, Andrew M. Tyrrell:
Real-time transputer simulation of the human peripheral hearing system. 215-221 - V. Lakshmi Narasimhan, A. C. Lewty:
Distributed event-driven simulation of a novel dynamic dataflow multiprocessor system - PATTSY. 223-230 - Dan R. McCutchan, James W. Reilly:
Pentium processor thermal design guidelines. 231-237
Volume 18, Number 5, June 1994
- Ezequiel Ballesteros, Francisco Lorenzo, T. Viera, Marcos Reyes, José A. Bonet:
Electronic design of a solar correlation tracker based on a video motion estimation processor. 243-251 - V. Lakshmi Narasimhan, K. Wood, Tom Downs:
A four-channel communications arbiter for multiprocessor arrays. 253-260 - K. V. Subramaniam, Matthew J. Thazhuthaveetil:
Design of an MS-DOS PC program profiler. 261-269 - Pavel Zemcík, Erik L. Dagless:
Printing grey scale images on a fax machine. 271-279 - Giuseppe De Pietro, Umberto Villano:
SYNC_WAVE: a high accuracy and low overhead algorithm for clock, synchronization in transputer networks. 281-290 - John Cooke:
Symbolic Model Checking: Kenneth L McMillan, Kluwer Academic, Dordrecht, The Netherlands (1993) ISBN 0 7923 9380 5, £54.50, pp 194. 297 - David McCartney:
68000 Family Assembly Language: Alan Clements, PWS Publishing, Boston, USA (1994) ISBN 0 534 93275 4, £20.95, pp 720. 298 - Dieter Gollmann:
Error Detecting Circuits: Michael Gössel and Steffen Graf, McGraw-Hill, Maidenhead, UK (1993) ISBN 0 07 707438 6, £35.00, pp 224. 298-299 - Padmanabhan Krishnan:
Corrigendum. 299
Volume 18, Number 6, 1994
- Nadarajah Sriskanthan, Amitabha Das, Peter K. K. Loh, Ang Hock Leong:
An adaptive switching architecture for multiprocessor networks. 307-314 - Teresa Sánchez, José Javier Anaya, Carlos Fritsch:
Performance of the IMS A100 digital signal processor for real-time deconvolution. 315-322 - N. Chen, Graham A. Parker:
Design of a robot control system architecture. 323-330 - Salvatore Cavalieri, Antonella Di Stefano, Orazio Mirabella:
Artificial neural networks on a reconfigurable, fault-tolerant, multi-processor system. 331-341 - Panagiotis Tzionas, Philippos Tsalides, Adonios Thanailakis:
A modified discrete Fourier-cosine transform algorithm and its VLSI implementation. 343-350 - Bob Fine, Gerald McGuire:
Considerations for selecting a DSP processor (ADSP-2101 vs. TMS320C50). 351-362 - Geof F. Carpenter:
Reliability in Instrumentation and Control: J C Cluley Butterworth-Heinemann, Oxford, UK (1993) ISBN 0 7506 0737 8, £25, pp 155. 363 - David Milford:
Programmable Logic Handbook (second edition): Geoff Bostock Butterworth-Heinemann, Oxford, UK (1993) ISBN 0 7506 0808 0, £19.95, pp 301. 363-364
Volume 18, Number 7, 1994
- Tatsuhiro Torii, Michael Singh Chelian:
A new fault-tolerant multitransputer configuration for avionics two-lane systems. 371-376 - M. Moshgbar, Robert M. Parkin:
An intelligent distributed system for real-time control of cone crushers. 377-383 - Jim E. Cooling, T. S. Hughes:
Making formal specifications accessible through the use of animation prototyping. 385-392 - Anand V. Hudli, Raghu V. Hudli:
Finding small feedback vertex sets for VLSI circuits. 393-400 - Yiu-Kwong Wong, Ahmad B. Rad:
Comparison of the performance of a fuzzy controller with a PID controller for a heating process. 401-407
Volume 18, Number 8, October 1994
- Martyn Edwards:
Logic synthesis. 427-428 - Tadeusz Luba:
Multi-level logic synthesis based on decomposition. 429-437 - A. J. W. M. ten Berg:
MASCOT: Microarchitecture synthesis of control paths. 439-449 - James Pardey, Alain Amroun, Martin Bolton, Marian Adamski:
Parallel controller synthesis for programmable logic devices. 451-457 - M. S. Abrahams, A. Rushton:
Translation of VHDL for logic synthesis. 459-467 - Otmar von Steuber, Hans Martin Lipp:
ARTUS - an open framework for logic synthesis. 469-472 - S. J. McIlroy, Noel E. Evans:
An encoding telemeter for climatic temperature monitoring using a single chip microcontroller. 473-479 - K. Vijayan Asari, C. Eswaran:
Systolic array implementation of artificial neural networks. 481-488 - Martin Bolton:
High-level synthesis : D D Gajaski, N D Dutt, A C-H Wu and S Y-L Lin Kluwer Academic Publishers, Dordrecht, The Netherlands (1992) ISBN 0 7923 9194 2, £62.95, pp 359. 489 - Martyn Edwards:
Logic synthesis and optimization : Edited by T Sasao Kluwer Academic Publishers, Dordrecht, The Netherlands (1993) ISBN 0 7923 9308 2, Dfl 181.25, £66.75, pp 375. 489-490 - Alain Amroun:
The synthesis approach to digital systems design : P Michel, U Lauther and P Duzy Kluwer Academic Publishers, Dordrecht, The Netherlands (1992) ISBN 0 7923 9199 3, £57.50, pp 432. 490-491 - David G. Hendry:
High level synthesis for real-time digital signal processing : J Vanhoof, K V Rompaey, I Bolsens, G Goossens and H De Man Kluwer Academic Publishers, Dordrecht, The Netherlands (1993) ISBN 0 792 393139, Dfl 177.00, £65.25, pp 302. 491-492
Volume 18, Number 9, 1994
- Jim E. Cooling:
Hard real-time embedded operating systems. 499-500 - Barbara Korousic-Seljak:
Task scheduling policies for real-time systems. 501-511 - Steven Bradley, William Henderson, David Kendall, Adrian Robson:
A formally based hard real-time kernel. 513-521 - Damjan Zazula, Andrej Sostaric, Danilo Korze, Dean Korosec:
Computer-assisted exercise ECG analysis: real-time scheduling within MS-DOS on PCs. 523-535 - Jens-Uwe Dzikowski, Peter Rounce:
Using databases to support the development of microcode. 537-546 - Bradly K. Fawcett:
System-integration features and development tools key to FPGA design. 547-560
Volume 18, Number 10, December 1994
- Jim E. Cooling:
Task scheduling in hard real-time embedded systems using hardware co-processors. 571-578 - Matjaz Colnaric, Wolfgang A. Halang, Ronald M. Tol:
A hardware supported operating system kernel for embedded hard real-time applications. 579-591 - Richard J. Mitchell, Martin J. Loomes, John Howse:
Structuring formal specifications - a lesson relearned. 593-599 - Koenraad M. R. Audenaert, Luk Levrouw:
Interrupt replay: a debugging method for parallel programs with interrupts. 601-612 - Anupama Hegde:
Error detection and correction with the IDT49C466. 613-620 - Marian Adamski:
Structured Logic Design with VHDL : James R Armstrong and F Gail Gray Prentice Hall International, Englewood Cliffs, NJ, USA (1993) ISBN 0 13 855206 I, £43.25, pp 482. 621-622 - M. Moshgbar:
Robot Learning : Edited by J H Connell and S Mahadevan Kluwer Academic, Dordrecht, The Netherlands (1993) ISBN 0 7923 9365 I, £65.75, Dfl.185.00, pp 256. 622
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2026-05-18 00:08 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
