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ORCIDACM Journal on Emerging Technologies in Computing Systems, Volume 14
Volume 14, Number 1, March 2018
- Neel Gala, Sarada Krithivasan, Wei-Yu Tsai, Xueqing Li, Vijaykrishnan Narayanan, V. Kamakoti:
An Accuracy Tunable Non-Boolean Co-Processor Using Coupled Nano-Oscillators. 1:1-1:28 - Mesbah Uddin
, Md. Badruddoja Majumder, Karsten Beckmann, Harika Manem, Zahiruddin Alamgir, Nathaniel C. Cady, Garrett S. Rose:
Design Considerations for Memristive Crossbar Physical Unclonable Functions. 2:1-2:23 - Ye Yu, Niraj K. Jha:
Statistical Optimization of FinFET Processor Architectures under PVT Variations Using Dual Device-Type Assignment. 3:1-3:25 - Mohammad Hossein Hajkazemi, Mohammad Khavari Tavana, Tinoosh Mohsenin, Houman Homayoun:
Heterogeneous HMC+DDRx Memory Management for Performance-Temperature Tradeoffs. 4:1-4:21 - Sukanta Bhattacharjee, Debasis Mitra, Bhargab B. Bhattacharya:
Robust In-Field Testing of Digital Microfluidic Biochips. 5:1-5:17 - Xiaokun Yang, Wujie Wen, Ming Fan:
Improving AES Core Performance via an Advanced ASBUS Protocol. 6:1-6:23 - Kenneth O'Neal, Daniel T. Grissom, Philip Brisk:
Resource-Constrained Scheduling for Digital Microfluidic Biochips. 7:1-7:26 - Seyedhamidreza Motaman, Swaroop Ghosh, Jaydeep P. Kulkarni:
Impact of Process Variation on Self-Reference Sensing Scheme and Adaptive Current Modulation for Robust STTRAM Sensing. 8:1-8:17 - Vincenzo Catania, Andrea Mineo, Salvatore Monteleone, Maurizio Palesi, Davide Patti:
Improving Energy Efficiency in Wireless Network-on-Chip Architectures. 9:1-9:24 - Bohua Li, Yukui Pei, Wujie Wen:
Efficient LDPC Code Design for Combating Asymmetric Errors in STT-RAM. 10:1-10:20 - Yu Liu, Yingyezhe Jin, Peng Li:
Online Adaptation and Energy Minimization for Hardware Recurrent Spiking Neural Networks. 11:1-11:21 - Paolo Grani, Sandro Bartolini:
Scalable Path-Setup Scheme for All-Optical Dynamic Circuit Switched NoCs in Cache Coherent CMPs. 12:1-12:27 - Andre van Rynbach, Muhammad Ahsan, Jungsang Kim:
A Quantum Computing Performance Simulator Based on Circuit Failure Probability and Fault Path Counting. 13:1-13:17
Volume 14, Number 2, July 2018
- Yu Cao, Xin Li, Jae-sun Seo, Ganesh Dasika:
Guest Editors' Introduction: Frontiers of Hardware and Algorithms for On-chip Learning. 14:1-14:2 - Hyungjun Kim, Taesu Kim, Jinseok Kim, Jae-Joon Kim:
Deep Neural Network Optimized to Resistive Memory with Nonlinear Current-Voltage Characteristics. 15:1-15:17 - Syed Shakib Sarwar, Swagath Venkataramani, Aayush Ankit, Anand Raghunathan, Kaushik Roy:
Energy-Efficient Neural Computing with Approximate Multipliers. 16:1-16:23 - Glenn G. Ko, Rob A. Rutenbar:
Real-Time and Low-Power Streaming Source Separation Using Markov Random Field. 17:1-17:22 - Yixing Li, Zichuan Liu, Kai Xu, Hao Yu, Fengbo Ren:
A GPU-Outperforming FPGA Accelerator Architecture for Binary Convolutional Neural Networks. 18:1-18:16 - Thomas E. Potok, Catherine D. Schuman, Steven R. Young, Robert M. Patton, Federico M. Spedalieri, Jeremy Liu, Ke-Thia Yao, Garrett S. Rose, Gangotree Chakma:
A Study of Complex Deep Learning Networks on High-Performance, Neuromorphic, and Quantum Computers. 19:1-19:21
- Jiang Xu, Yuichi Nakamura, Andrew B. Kahng:
Silicon Photonics for Computing Systems. 20 - Zhe Zhang, Yaoyao Ye:
A Learning-Based Thermal-Sensitive Power Optimization Approach for Optical NoCs. 21 - Yi Xu, Jun Yang, Rami G. Melhem:
A Process-Variation-Tolerant Method for Nanophotonic On-Chip Network. 22:1-22:23 - Edoardo Fusella, Alessandro Cilardo:
Reducing Power Consumption of Lasers in Photonic NoCs through Application-Specific Mapping. 23:1-23:11 - Jiating Luo, Cédric Killian, Sébastien Le Beux, Daniel Chillet, Olivier Sentieys, Ian O'Connor:
Offline Optimization of Wavelength Allocation and Laser Power in Nanophotonic Interconnects. 24:1-24:19 - Scott Vanwinkle, Avinash Karanth Kodi:
SHARP: Shared Heterogeneous Architecture with Reconfigurable Photonic Network-on-Chip. 25:1-25:22 - Tohru Ishihara, Akihiko Shinya, Koji Inoue, Kengo Nozaki, Masaya Notomi:
An Integrated Nanophotonic Parallel Adder. 26:1-26:20 - Shi Xu, Zhang Luo, Mingche Lai, Zhengbin Pang, Renfa Li:
Integrated High-Speed Optical SerDes over 100GBd Based on Optical Time Division Multiplexing. 27:1-27:16
- Ali Alsuwaiyan, Kartik Mohanram:
MFNW: An MLC/TLC Flip-N-Write Architecture. 28:1-28:32 - Shuai Chen, Junlin Chen, Lei Wang:
A Chip-Level Anti-Reverse Engineering Technique. 29:1-29:20 - Debjyoti Bhattacharjee, Anne Siemon, Eike Linn, Stephan Menzel, Anupam Chattopadhyay:
Kogge-Stone Adder Realization using 1S1R Resistive Switching Crossbar Arrays. 30:1-30:14 - Florian Neugebauer, Ilia Polian, John P. Hayes:
Framework for Quantifying and Managing Accuracy in Stochastic Circuit Design. 31:1-31:21
Volume 14, Number 3, October 2018
- Dongjin Lee, Sourav Das, Dae Hyun Kim, Janardhan Rao Doppa, Partha Pratim Pande:
Design Space Exploration of 3D Network-on-Chip: A Sensitivity-based Optimization Approach. 32:1-32:26 - Xiaotong Cui, Elnaz Koopahi, Kaijie Wu, Ramesh Karri:
Hardware Trojan Detection Using the Order of Path Delay. 33:1-33:23 - Guan-Ruei Lu, Ansuman Banerjee, Bhargab B. Bhattacharya, Tsung-Yi Ho, Hung-Ming Chen:
Reliability Hardening Mechanisms in Cyber-Physical Digital-Microfluidic Biochips. 34:1-34:22 - Farhana Parveen, Shaahin Angizi, Deliang Fan:
IMFlexCom: Energy Efficient In-Memory Flexible Computing Using Dual-Mode SOT-MRAM. 35:1-35:18 - Edgard Muñoz-Coreas, Himanshu Thapliyal:
T-count and Qubit Optimized Quantum Circuit Design of the Non-Restoring Square Root Algorithm. 36:1-36:15 - Ayed Alqahtani, Zongqing Ren, Jaeho Lee, Nader Bagherzadeh:
System-Level Analysis of 3D ICs with Thermal TSVs. 37:1-37:16 - Nihar Athreyas, Wenhao Song, J. Blair Perot, Qiangfei Xia, Abbie Mathew, Jai Gupta, Dev Gupta, J. Joshua Yang:
Memristor-CMOS Analog Coprocessor for Acceleration of High-Performance Computing Applications. 38:1-38:30
Volume 14, Number 4, December 2018
- Guest Editor Introduction: Neuromorphic Computing. 39:1-39:3
- Kathleen E. Hamilton, Neena Imam, Travis S. Humble:
Sparse Hardware Embedding of Spiking Neuron Systems for Community Detection. 40:1-40:13 - Venkata Ramesh Bontupalli, Chris Yakopcic, Raqibul Hasan, Tarek M. Taha:
Efficient Memristor-Based Architecture for Intrusion Detection and High-Speed Packet Classification. 41:1-41:27 - Kyungwook Chang, Deepak Kadetotad, Yu Cao, Jae-sun Seo, Sung Kyu Lim:
Power, Performance, and Area Benefit of Monolithic 3D ICs for On-Chip Deep Neural Networks Targeting Speech Recognition. 42:1-42:19 - Abdullah M. Zyarah, Dhireesha Kudithipudi:
Semi-Trained Memristive Crossbar Computing Engine with In Situ Learning Accelerator. 43:1-43:16 - Gopalakrishnan Srinivasan, Priyadarshini Panda, Kaushik Roy:
STDP-based Unsupervised Feature Learning using Convolution-over-time in Spiking Neural Networks for Energy-Efficient Neuromorphic Computing. 44:1-44:12 - Kangjun Bai, Yang Yi:
DFR: An Energy-efficient Analog Delay Feedback Reservoir Computing System for Brain-inspired Computing. 45:1-45:22 - Lisa Loomis, Nathan McDonald, Cory E. Merkel:
An FPGA Implementation of a Time Delay Reservoir Using Stochastic Logic. 46:1-46:15 - Zhongyang Liu, Shaoheng Luo, Xiaowei Xu, Yiyu Shi, Cheng Zhuo:
A Multi-Level-Optimization Framework for FPGA-Based Cellular Neural Network Implementation. 47:1-47:17 - Xiaowei Xu, Qing Lu, Tianchen Wang, Yu Hu, Chen Zhuo, Jinglan Liu, Yiyu Shi:
Efficient Hardware Implementation of Cellular Neural Networks with Incremental Quantization and Early Exit. 48:1-48:20
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