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ORCIDInternational Journal of High Performance Systems Architecture, Volume 5
Volume 5, Number 1, 2014
- Yamin Wen, Zheng Gong:
Private mutual authentications with fuzzy matching. 3-12 - Yongmei Xu, Yuihui Deng, Lan Du:
Computing the PUE of data centres by leveraging workload fluctuation. 13-18 - Yan Ren, Yunhong Hu, Hongbin Wang:
On provably secure code-based multiple grade proxy signature scheme. 19-24 - Changjiang Hou, Fei Liu, Hongtao Bai, Lanfang Ren:
Public-key searchable encryption from lattices. 25-32 - Chundong Wang, Guangming Bo:
A novel approach to generate and extract audio watermark. 33-38 - Jian Zhang, Renhong Cheng, Kai Wang, Hong Zhao:
Research on born-digital image text extraction based on conditional random field. 39-49 - Yiqiao Cai, Ji-Xiang Du, Weibin Chen:
Enhancing the search ability of differential evolution through competent leader. 50-62 - Quan Zhou, Daixian Wu, Chunming Tang, Chunming Rong
:
STSHC: secure and trusted scheme for Hadoop cluster. 63-69
Volume 5, Number 2, 2014
- Mahnaz Rafie, Ahmad Khademzadeh, Midia Reshadi:
Performance improvement of application-specific network on chip using machine learning algorithms. 71-83 - Yaobin Wang, Zhiqin Liu, Huarong Chen, Xia Luo, Guotang Bi, Hong An:
Exploring speculative procedure and loop level parallelism in SPLASH2. 84-92 - Hameedah Sultan, Gayathri Ananthanarayanan, Smruti R. Sarangi:
Processor power estimation techniques: a survey. 93-114 - Junneng Zhang, Chao Wang, Xi Li, Xuehai Zhou, Aili Wang, Gangyong Jia, Nadia Nedjah:
Amdahl's and Hill-Marty laws revisited for FPGA-based MPSoCs: from theory to practice. 115-126
Volume 5, Number 3, 2015
- S. P. Joy Vasantha Rani:
Pipelined hardware design of self tuning controller with on-chip parameter estimator. 127-140 - Kanchan Manna, Chakradhar Reddy Veeramreddy, Santanu Chattopadhyay, Indranil Sengupta:
Thermal-aware multifrequency network-on-chip testing using particle swarm optimisation. 141-152 - Shirin Rezaie, Reza Faghih Mirzaee, Keivan Navi, Omid Hashemipour:
New dynamic ternary minimum and maximum circuits with reduced switching activity and without any additional voltage sources. 153-165 - Arun Parakh, M. Balakrishnan, Kolin Paul:
Improving Map-Reduce for GPUs with cache. 166-177 - Yaroub Elloumi, Mohamed Akil, Mohamed Hedi Bedoui:
Execution time optimisation using delayed multidimensional retiming. 178-191
Volume 5, Number 4, 2015
- Yavar Safaei Mehrabani, Reza Faghih Mirzaee, Mohammad Eshghi:
A novel low-energy CNFET-based full adder cell using pass-transistor logic. 193-201 - Somaye Mohammadyan, Shaahin Angizi, Keivan Navi:
New fully single layer QCA full-adder cell based on feedback model. 202-208 - Mohammad Hossein Moaiyeri, Mohsen Shamohammadi, Fazel Sharifi, Keivan Navi:
High-performance ternary logic gates for nanoelectronics. 209-215 - Mageda Sharafeddine, Haitham Akkary:
A small and power efficient checkpoint core architecture for manycore processors. 216-227 - Huang Wang, Chao Wang, Huaping Chen:
XEMU: a cross-ISA full-system emulator on multiple processor architectures. 228-239 - Mohammed kamel Benhaoua, Amit Kumar Singh:
Dynamic communications mapping in multi-tasks NoC-based heterogeneous MPSoCs platform. 240-251
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