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ORCIDInternational Journal of High Performance Systems Architecture, Volume 3
Volume 3, Number 1, 2011
- Peng Liu, Yangfan Liu, Bingjie Xia, Chunchang Xiang, Xiaohang Wang, Kejun Wu, Weidong Wang, Qingdong Yao:
A networks-on-chip emulation/verification framework. 2-11 - Akira Hatanaka, Nader Bagherzadeh
:
A scheduling approach for distributed resource architectures with scarce communication resources. 12-22 - Ashwini Raina, Venkatesan Muthukumar:
A unified design space simulation environment for network-on-chip: fuse-N. 23-32 - Makoto Ozone, Tatsuo Hiramatsu, Katsunori Hirase, Kazuhisa Iizuka, Shin-ichiro Tomisawa:
Reconfigurable processor based on ALU array architecture for software radio. 33-40 - Edson Pedro Ferlin, Heitor S. Lopes, Carlos Raimundo Erig Lima, Mauricio Perretto:
PRADA: a high-performance reconfigurable parallel architecture based on the dataflow model. 41-55 - Amir Hosseini, Vahid Shabro:
Electromigration-aware dynamic routing algorithm for network-on-chip applications. 56-63
Volume 3, Numbers 2/3, 2011
- Jorge Tortato Junior, Roberto A. Hexsel:
A minimalist cache coherent MPSoC designed for FPGAs. 67-76 - Stefano Drimon Kurz Mor, Nicolas Maillard:
Dynamic workload balancing deques for branch and bound algorithms in the message passing interface. 77-86 - Alvaro Luiz Fazenda, Jairo Panetta, Daniel M. Katsurayama, Luiz Flavio Rodrigues, Luis F. G. Motta, Philippe Olivier Alexandre Navaux:
Challenges and solutions to improve the scalability of an operational regional meteorological forecasting model. 87-97 - Bruno Batista Boniati, Andrea Schwertner Charão, Benhur de Oliveira Stein, Gustavo Rissetti, Eduardo Kessler Piveta:
Automated refactorings for high performance Fortran programmes. 98-109 - Fernando Kronbauer, Sandro Rigo:
Assessing the influence of data access patterns and contention management policies on the performance of software transactional memory systems. 110-121 - Francieli Zanon Boito, Rodrigo Virote Kassick, Philippe Olivier Alexandre Navaux:
The impact of applications' I/O strategies on the performance of the Lustre parallel file system. 122-136 - Tiago A. O. Alves, Leandro A. J. Marzulo, Felipe M. G. França, Vítor Santos Costa:
Trebuchet: exploring TLP with dataflow virtualisation. 137-148 - Mahzad Azarmehr, Roberto Muscedere:
A RISC architecture for 2DLNS-based signal processing. 149-156 - Ling Wang, Chunda Ding, Shenghai Zhong, Jianwen Zhang:
GNLS: a hybrid on-chip communication architecture for SoC designs. 157-166 - Marcos Santana Farias, Nadia Nedjah, Luiza de Macedo Mourelle:
A hardware architecture for subtractive clustering. 167-173
Volume 3, Number 4, 2011
- Mohamed Issad, Mohamed Anane, Nadjia Anane:
An optimised architecture for radix-2 Montgomery modular multiplication on FPGA. 175-183 - D. Meganathan:
A 24.5 mW, 10-bit, 50 MS/sec CMOS pipelined analogue-to-digital converter. 184-201 - Anubis Graciela de Moraes Rossetto, Carlos Oberdan Rolim, Valderi R. Q. Leithardt, Mario A. R. Dantas, Cláudio F. R. Geyer:
An adaptive fault tolerance approach to enhance the execution of applications on multi-cluster grid configurations from mobile grid interfaces in wireless networks. 202-215 - Mais Nijim, Xiao Qin, Muhittin Yilmaz:
CaPaS: an optimal security-aware cache replacement algorithm for cluster storage systems. 216-232 - Rogério De Moraes Calazan, Nadia Nedjah, Luiza de Macedo Mourelle:
Parallel co-processor for PSO. 233-240
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