default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID7th SLIP 2005: San Francisco, CA, USA
- Igor L. Markov, Mike Hutton:
The Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings. ACM 2005, ISBN 1-59593-033-7
Interconnect scaling
- Ron Ho:
High-performance ULSI: the real limiter to interconnect scaling. 3
Interconnect optimization
- Takumi Uezono, Junpei Inoue, Takanori Kyogoku, Kenichi Okada, Kazuya Masu:
Prediction of delay time for future LSI using on-chip transmission line interconnects. 7-12 - Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, Philippe M. Fauchet, Eby G. Friedman, David H. Albonesi:
Predictions of CMOS compatible on-chip optical interconnect. 13-20 - J. Balachandran, Steven Brebels, Geert Carchon, Tomas Webers, Walter De Raedt
, Bart Nauwelaers, Eric Beyne:
Package level interconnect options. 21-27 - Katherine Shu-Min Li, Chung-Len Lee, Yao-Wen Chang, Chauchin Su, Jwu E. Chen:
Multilevel full-chip routing with testability and yield enhancement. 29-36
Interconnect variation
- N. S. Nagaraj:
Dealing with interconnect process variations. 39
Interconnect prediction
- Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand:
Predicting interconnect requirements in ultra-large-scale integrated control logic circuitry. 43-50 - Wim Heirman, Joni Dambre, Christof Debaes, Hugo Thienpont, Dirk Stroobandt, Jan Van Campenhout:
Prediction model for evaluation of reconfigurable interconnects in distributed shared-memory systems. 51-58
Power and noise
- David J. Hathaway:
Dealing with the spatio-temporal interactions among transient power, supply noise and timing. 61
Interconnect in three dimensions
- Young-Su Kwon, Payam Lajevardi, Anantha P. Chandrakasan, Frank Honoré, Donald E. Troxel:
A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool. 65-72 - Viet H. Nguyen, Phillip Christie:
The impact of interstratal interconnect density on the performance of three-dimensional integrated circuits. 73-78
Design issues for interconnect
- Jens Lienig:
Interconnect and current density stress: an introduction to electromigration-aware design. 81-88
nterconnect congestion estimation
- Chiu-Wing Sham, Evangeline F. Y. Young:
Congestion prediction in early stages. 91-98 - Jurjen Westra, Patrick Groeneveld:
Is probabilistic congestion estimation worthwhile? 99-106
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2026-04-27 01:19 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
