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ORCID37th SBCCI 2024: Joao Pessoa, Brazil
- 37th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design, SBCCI 2024, Joao Pessoa, Brazil, September 2-6, 2024. IEEE 2024, ISBN 979-8-3503-9169-5
- Arthur M. Fortini, João Gabriel O. Bicalho, Omar P. Vilela Neto, Maria D. Vieira, José Augusto Miranda Nacif, Ricardo S. Ferreira
:
Robustness Analysis of Atomic Silicon Quantum Dot Logic Gates. 1-5 - Vanessa M. Da F. Botinelly, Filipe F. Caetano, Pietro M. Ferreira, Osamu Saotome, Lucas Compassi Severo:
Design of Low-Power 5.8-GHz ULV LNTAs using Normalized Biasing Metric. 1-5 - Leonardo R. Gobatto, Fabio Benevenuti, Rodrigo Possamai Bastos, Fernanda Lima Kastensmidt, José Rodrigo Azambuja:
Early Neutron Reliability Assessment of an Arm Cortex-M4 through Emulated Fault Injection. 1-5 - Pedro Toledo, Sergio Bampi, Paolo Crovetti:
The Digital-Based Operational Transconductance Amplifier: Evolution and Perspective. 1-7 - Jelson Rodrigues, Jones Goebel, Luciano Agostini, Bruno Zatt, Marcelo Schiavon Porto:
Bit-Width Optimized Transposition Buffer Design for the AV1 2D-DCT Transform. 1-5 - Thalis Da C. Guedes, Johan Bourgeat, Manuel J. Barragán, Jean-Marc Duchamp, Philippe Ferrari:
Design and Evaluation of a 10 GHz LNA with Balun and Diodes for HBM and CDM ESD Protection in 28 nm CMOS FD-SOI. 1-5 - Julio Costella Vicenzi, Michael G. Jordan, Guilherme Korol, Tiago Knorst, Mateus Beck Rutzig, Antonio Carlos Schneider Beck:
TARA: Enhancing Real-Time Network Traffic Classification with Hardware Virtual Layers. 1-5 - Bernardo N. Gomes, Marco T. D. Sousa, Jeferson F. Chaves, Omar P. Vilela Neto:
An evolutionary search for energy recovery opportunities in partially reversible FCN circuits. 1-5 - Thiago Dos Santos Gonçalves, Antonio Carlos Schneider Beck, Arthur Francisco Lorenzon:
Investigating the Influence of Process Variability on Asymmetric Multicore Processors. 1-5 - Denis Maass, Marcello M. Muñoz, Murilo R. Perleberg, Luciano Agostini, Marcelo Schiavon Porto:
A Real-Time UHD 4K Hardware for VVC Affine Linear Equation System Solving. 1-5 - Victor R. R. de Oliveira, Mirella M. de O. Carneiro, Fernanda D. V. R. Oliveira, Fernando Antonio Pinto Barúqui, José Gabriel R. C. Gomes:
Layout Design of an Asynchronous Time-Based Image Sensor with Shared DVS Module. 1-5 - Anderson R. P. Domingues, Lucas Damo, Sergio Johann Filho, Fernando Gehm Moraes:
Joint Computation and Communication Analysis of Hard Real-Time Applications in Manycores. 1-5 - Nataly Pozo, Luis-Miguel Prócel, Lionel Trojman:
All-GaN Integrated Overcurrent Protection Circuit Using Only Enhancement-mode p-GaN Devices. 1-5 - Lucas Daudt Franck, João Navarro, João Paulo Carmo:
A Divide-by-1.5/2 Prescaler Utilizing Double Data Rate Technique. 1-5 - Renan D. P. de Oliveira, Tawan Chrysther dos Santos, Matheus B. S. Carvalho, Crístian Müller, Alessandro Gonçalves Girardi, Lucas Compassi Severo, Paulo César Comassetto de Aguirre:
A 5-V 125-kHz Fourth-Order Continuous-Time Sigma-Delta Modulator in 130-nm BCD Technology. 1-5 - Eduardo Marañon Aguilar, Fabio Benevenuti, Fernanda Lima Kastensmidt:
Hardening a RISC-V Softcore for Embedded Aerospace Applications in SRAM-based FPGA. 1-5 - Nathan Guimarães, Mateus Saquetti, Pablo Rodrigues, Weverton Cordeiro, José Rodrigo Azambuja:
Enabling Programmable Data Planes with C++ and High-Level Synthesis for Custom Packet Forwarding. 1-5 - Ana Italiano, Luciana Faletti Almeida, Thiago Brito, Mariane R. Petraglia, Fabián Olivera:
EAVREF: An Evolutionary Algorithm Based Tool for Low-Power CMOS Voltage Reference Designs. 1-5 - Angelo Elias Dalzotto, Fernando Gehm Moraes:
A Machine Learning Approach for Traffic Anomaly Detection in NoC-based Manycores. 1-5 - Iaçanã I. Weber, Vitor Balbinot Zanini, Fernando Gehm Moraes:
Enhancing Manycore Lifetime Through Reinforcement Learning Task Mapping and Migration. 1-5 - Luís Fernando Miki, Laysson Oliveira Luz, José Augusto Miranda Nacif, Ricardo S. Ferreira, Omar P. Vilela Neto:
A Nanomagnetic Logic based processor. 1-5 - Marcelo K. Moori, Hiago Mayk G. de A. Rocha, Arthur Francisco Lorenzon, Antonio Carlos Schneider Beck:
Efficient Thread Tuning for Asymmetric Multicores. 1-5 - Luiz Fernando Heidrich Duarte, George B. Nardes, Wesley Grignani, Douglas R. Melo, Cesar A. Zeferino:
Deep Nibble: A 4-bit Number Format for Efficient DNN Training and Inference in FPGA. 1-5 - Lourenço Mulling, Morgana Macedo Azevedo da Rosa, Rafael Soares, Eduardo A. C. da Costa:
AxMOD: VLSI Modular Reduction Design Exploring Approximate Arithmetic Units. 1-5 - Léo Ribeiro, Morgana Macedo Azevedo da Rosa, Rafael Soares, Eduardo A. C. da Costa:
Exploring Approximate Adders for an Energy-Efficient Pre-Processing Pan-Tompkins Algorithm VLSI Design. 1-5 - Esther Goudet, Luis Peña Treviño, Gutemberg G. dos Santos Júnior, Sayah El Hajji, Fabio Sureau, Lirida Naviner, Jean-Marc Daveau, Philippe Roche:
Drift of Combinational Circuits Failure Rates with a Probabilistic Model Approximated by Partitioning. 1-5 - Anderson I. Silva, Altamiro Susin, Fernanda L. Kastensmidt, Antonio Carlos S. Beck, José Rodrigo Azambuja:
NoX: a Compact Open-Source RISC-V Processor for Multi-Processor Systems-on-Chip. 1-5 - Jorge Angarita Pérez, Nicolas Orcasitas García, Hugo D. Hernández, Javier Ardila:
A 9.78-ENOB 10 MS/s SAR ADC with a Common Mode Compensation Technique in a 28nm CMOS Node. 1-5 - Arthur F. Ely, Fabio Benevenuti, Guilherme Korol, Antonio Carlos S. Beck, José Rodrigo Azambuja, Fernanda Lima Kastensmidt:
Image Classification CNNs using the FINN Engine for SRAM-based APSoC in Satellite Applications. 1-5 - Ian Kersz, Henry R. Piceni, Michael G. Jordan, José Rodrigo Azambuja, Fernanda Lima Kastensmidt, Antonio Carlos S. Beck:
ADARE: Adaptive Resource Provisioning in Multi-FPGA Edge Environments. 1-5 - João Carlos Prats Ramos, Naiara Sachetti, Augusto Andre Souza Berndt, Jônata Tyska Carvalho, Cristina Meinhardt:
Impact on Delay, Power and Area of Machine Learning-based Approximate Logic Synthesis. 1-5 - Victor Sberse Guerra, Gabriel Luca Nazar:
FPGAs for Network Function Virtualization: Challenges in Placement and Partitioning. 1-5 - Rodrigo S. Moraes, Lucas Compassi Severo:
A Semi-Automated Sizing Tool for CMOS Analog Building Blocks Integrated into EDA Environment. 1-5 - Leonardo Augusto, Thiago L. T. da Silveira, Mateus Grellert:
Computationally-Efficient Neural Image Compression Using Asymmetric Autoencoders. 1-5 - Zhenghan Fang, Lirida Naviner, Wen Wang, Wei Le, Hao Cai:
Towards Reliability MRAM for Energy-Efficient Spin-orbit Torque Switching. 1-5 - Ramiro Viana, Marta Loose, Rafael S. Ferreira, Marcelo Schiavon Porto, Guilherme Corrêa, Luciano Agostini:
A Hardware-Friendly Acceleration of VVC Affine Motion Estimation Using Decision Trees. 1-5 - Tawan Chrysther dos Santos, Alessandro Gonçalves Girardi, Paulo César Comassetto de Aguirre:
Voltage Coefficient of Resistance Effect in the Harmonic Distortion of Active-RC Continuous-Time Sigma-Delta Modulators. 1-5 - Eloisa Barros, Morgana Macedo Azevedo da Rosa, Rodrigo Lopes, Leonardo Antonietti, Eduardo A. C. da Costa, Rafael Soares:
Evaluating the Resilience of the Approximate Parallel Prefix Adder (AxPPA) Against Hardware Trojan Horse Injection. 1-5 - Marcio Monteiro, Ismael Seidel, José Luís Güntzel, Mateus Grellert, Leonardo Bandeira Soares, Cristina Meinhardt:
A Dual-Kernel Size-Configurable Gaussian Filter Architecture. 1-5
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