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ORCID30th SBCCI 2017: Fortaleza - Ceará, Brazil
- Jarbas A. N. Silveira:
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, SBCCI 2017, Fortaleza, Ceará, Brazil, August 28 - September 01, 2017. ACM 2017, ISBN 978-1-4503-5106-5
Analog and radio frequency I
- Adriano V. Fonseca, Rachid El Khattabi, William A. Afshari, Fernando A. P. Barúqui, Carlos Fernando Teodósio Soares, Pietro Maris Ferreira
:
A temperature-aware analysis of latched comparators for smart vehicle applications. 1-6 - Julien Orlando, Francois Rivet, Yann Deval:
A radio-frequency real-time spectrum sensor based on an analog signal processing magnitude calculator. 7-10 - Nelson Andrade, Pedro Toledo, Gabriel Teofilo Neves Guimaraes, Hamilton Klimach, Helga Dornelas, Sergio Bampi:
Low power IEEE 802.11ah receiver system-level design aiming for IoT applications. 11-16 - Francelino Freitas Carvalho, Alexandre Kennedy Pinto Souza, Carlos Augusto de Moraes Cruz:
A novel hybrid polarization-quadrature pixel cluster for local light angle and intensity detection. 17-23 - Antonio C. C. Telles, Jose Antenor Pomilio, Saulo Finco:
Modeling of a MOS ultralow voltage oscillator: experimental results. 24-29
Digital circuits, mixed signal and applications I
- Camila de Matos Alonso, Fábio Luís Livi Ramos, Bruno Zatt, Marcelo Schiavon Porto, Sergio Bampi:
Low-power HEVC binarizer architecture for the CABAC block targeting UHD video processing. 30-35 - Gustavo Sanchez, Filipo Novo Mór, Luciano Volcan Agostini, César A. M. Marcon:
Low-area scalable hardware architecture for DMM-1 encoder of 3D-HEVC video coding standard. 36-40 - Luana Vieira Martinez Bonatto, Fábio Luís Livi Ramos, Bruno Zatt, Marcelo Schiavon Porto, Sergio Bampi:
Low-power multi-size HEVC DCT architecture proposal for QFHD video processing. 41-46 - Fábio Luís Livi Ramos, Bruno Zatt, Marcelo Schiavon Porto, Sergio Bampi:
Novel multiple bypass bins scheme for low-power UHD video processing HEVC binary arithmetic encoder architecture. 47-52 - Lucas F. S. Cambuim, João Paulo Fernandes Barbosa, Edna Natividade da Silva Barros:
Hardware module for low-resource and real-time stereo vision engine using semi-global matching approach. 53-58
SoC, NoC and reconfigurable
- Johanna Sepúlveda, Ramon Fernandes, César A. M. Marcon, Daniel Florez, Georg Sigl:
A security-aware routing implementation for dynamic data protection in zone-based MPSoC. 59-64 - Luciano L. Caimi, Vinicius Fochi, Eduardo Wächter, Daniel Munhoz, Fernando Gehm Moraes:
Secure admission and execution of applications in many-core systems. 65-71 - Ronaldo T. P. Milfont, Rafael Goncalves Mota, João Marcelo Ferreira, Paulo César Cortez, César A. M. Marcon, Daniel A. B. Tavares, Jarbas A. N. Silveira:
Latency reduction of fault-tolerant NoCs by employing multiple paths. 72-78 - Felipe T. Bortolon, Fernando Gehm Moraes:
Hardware and software infrastructure to implement many-core systems in modern FPGAs. 79-83
Embedded software and systems
- Ádria Barros de Oliveira, Gennaro Severino Rodrigues, Fernanda Lima Kastensmidt:
Analyzing lockstep dual-core ARM cortex-A9 soft error mitigation in freeRTOS applications. 84-89 - Felipe T. Bortolon, Fernando Gehm Moraes, Matheus T. Moreira, Sergio Bampi:
Estimation methods for static noise margins in CMOS subthreshold logic circuits. 90-95 - Carlos Eduardo dos Santos, Leandro dos Santos Coelho, Renato Coral Sampaio, Ricardo P. Jacobi, Helon V. H. Ayala, Carlos H. Llanos:
A SVM optimization tool and FPGA system architecture applied to NMPC. 96-102 - Ricardo A. Guazzelli, Matheus T. Moreira, Walter Lau Neto, Ney Laert Vilar Calazans:
Sleep convention logic isochronic fork: an analysis. 103-109
Analog and radio frequency II
- Tony Hanna, Nathalie Deltimple, Sébastien Fregonese:
A class-J power amplifier for 5G applications in 28nm CMOS FD-SOI technology. 110-113 - Hatem Ghaleb, Guido Belfiore, Corrado Carta, Frank Ellinger:
A SiGe HBT limiting amplifier for fast switching of mm-wave super-regenerative oscillators. 114-119 - Victor Vaillant, François Rivet:
An analog RF fully differential common mode controlled delay line in 28nm FDSOI technology. 120-124 - M. M. Rocha, Antonio C. C. Telles, Ricardo Cotrin Teixeira:
Development of microtransformers using MCM and electronic packaging technologies. 125-128 - Paolo Valerio Testa, Manu Viswambharan Thayyil, Guido Belfiore, Corrado Carta, Frank Ellinger:
High-impedance multi-conductor transmission-lines for integrated applications at millimeter-wave frequency. 129-135
Digital circuits, mixed signal and applications II
- Pablo Nunes Agra Belmonte, L. M. Chaves, Davies William de Lima Monteiro:
A pixel concept that simultaneously enables high dynamic range, high sensitivity and operation in intense backgrounds. 136-142 - Alex Borges, Luciano Almeida Braatz, Bruno Zatt, Marcelo Schiavon Porto, Guilherme Corrêa:
Segmented spline hardware design for high dynamic range video pre-processor. 143-148 - Luiz Henrique Cancellier, Ismael Seidel, José Luís Güntzel:
Block matching hardware architecture for SATD-based successive elimination. 149-154 - André Beims Bräscher, Ismael Seidel, José Luís Güntzel:
Improving the energy efficiency of a low-area SATD hardware architecture using fine grain PDE. 155-161 - Oscar Anacona-Mosquera, George Teodoro, Gustavo Vinhal, Ricardo P. Jacobi, Renato Coral Sampaio, Carlos H. Llanos:
Efficient hardware implementation of morphological reconstruction based on sequential reconstruction algorithm. 162-167
Digital circuits, mixed signal and applications III
- Guilherme Paim, Rafael S. Ferreira, Leandro M. G. Rocha, Eduardo A. C. da Costa, Tiago Giacomelli Alves, Sergio Bampi:
A power-predictive environment for fast and power-aware ASIC-based FIR filter design. 168-173 - Amanda F. Fonseca, Douglas L. Willian, Thiago Rodrigues B. S. Soares, Luiz G. C. Melo, Omar P. Vilela Neto:
CAM/TCAM - NML: (ternary) content addressable memory implemented with nanomagnetic logic. 174-179 - Felipe Makara, Lucas Mangini, André Augusto Mariano:
A 34fJ/conversion-step 10-bit 6.66MS/s SAR ADC with built-in digital calibration in 130nm CMOS. 180-184 - Jens Spinner, Jürgen Freudenberger:
A decoder with soft decoding capability for high-rate generalized concatenated codes with applications in non-volatile flash memories. 185-190
EDA/CAD, test and reliability
- Tiago Augusto Fontana, Sheiny Almeida, Renan Netto, Vinicius S. Livramento, Chrystian Guth, Laércio Lima Pilla, José Luís Güntzel:
Exploiting cache locality to speedup register clustering. 191-197 - Felipe G. A. e Silva, Otávio A. de Lima, Walter da C. Freitas, Fabian Vargas, Jarbas Silveira, César A. M. Marcon:
An efficient, low-cost ECC approach for critical-application memories. 198-203 - Luiz Henrique Borges Sardinha, Omar Paranaiba Vilela Neto, Vitor Buxbaum Orlandi, Sérgio Vale Aguiar Campos:
Simplified model for automatic QCA circuitry verification. 204-209 - Andrei Silva, Frank Sill:
Mitigation of aging effects through selective time-borrowing and alternative path activation. 210-216
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