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ORCID8. SASP 2010: Anaheim, California, USA
- IEEE 8th Symposium on Application Specific Processors, SASP 2010, Anaheim, CA, USA, June 13-14, 2010. IEEE Computer Society 2010, ISBN 978-1-4244-7952-8
- Ji Kong, Peilin Liu, Xianmin Chen, Jin Wang, Xingguang Pan, Jun Wang, He Xiao, Zhenqi Wei, Rendong Ying:
Next-generation consumer audio application specific embedded processor. 1-7 - Dominik Auras, Sylvain Girbal
, Hugues Berry, Olivier Temam, Sami Yehia:
CMA: Chip multi-accelerator. 8-15 - Ruby B. Lee, Yu-Yuan Chen:
Processor accelerator for AES. 16-21 - Michael Steffen, Joseph Zambreno:
A hardware pipeline for accelerating ray traversal algorithms on streaming processors. 22-29 - David Novo, Angeliki Kritikakou, Praveen Raghavan, Liesbet Van der Perre, Jos Huisken, Francky Catthoor:
Ultra low energy Domain Specific Instruction-set Processor for on-line surveillance. 30-35 - Jason Loew, Dmitry Ponomarev, Patrick H. Madden:
Customized architectures for faster route finding in GPS-based navigation systems. 36-43 - Ahmed O. El-Rayis, Tughrul Arslan, Ahmet T. Erdogan:
A processing engine for GPS correlation. 44-49 - Pei Liu, Ahmed Hemani:
A Coarse Grain Reconfigurable Architecture for sequence alignment problems in bio-informatics. 50-57 - Naotaka Maruyama, Tohru Ishihara, Hiroto Yasuura:
An RTOS in hardware for energy efficient software-based TCP/IP processing. 58-63 - Yi Shan, Tianji Wu, Yu Wang, Bo Wang, Zilong Wang, Ningyi Xu, Huazhong Yang:
FPGA and GPU implementation of large scale SpMV. 64-70 - Antonino Tumeo, Oreste Villa:
Accelerating DNA analysis applications on GPU clusters. 71-76 - Nicholas Moore, Miriam Leeser, Laurie A. Smith King:
Efficient template matching with variable size templates in CUDA. 77-80 - Mathew Paul, Peter Petrov:
I-cache configurability for temperature reduction through replicated cache partitioning. 81-86 - Thomas Marconi, Jae Young Hur, Koen Bertels, Georgi Gaydadjiev:
A novel configuration circuit architecture to speedup reconfiguration and relocation for partially reconfigurable devices. 87-92 - Khodor Ahmad Fawaz, Tughrul Arslan, Sami Khawam, Mark Muir, Ioannis Nousias, Iain Lindsay, Ahmet T. Erdogan:
A dynamically reconfigurable asynchronous processor. 93-96 - Dan Upton, Kim M. Hazelwood:
Design of a custom VEE core in a chip multiprocessor. 97-100 - Jingtong Hu, Chun Jason Xue, Wei-Che Tseng, Qingfeng Zhuge, Edwin Hsing-Mean Sha:
Minimizing write activities to non-volatile memory via scheduling and recomputation. 101-106 - Jelena Trajkovic, Daniel D. Gajski:
Early performance-cost estimation of application-specific data path pipelining. 107-110 - Jer-Min Jou, Yun-Lung Lee, Sih-Sian Wu:
Efficient design and generation of a multi-facet arbiter. 111-114 - Hui-Shan Wang, I-Wei Wu, Jean Jyh-Jiun Shann, Chung-Ping Chung:
Reconfigurable custom functional unit generation and exploitation in multiple-issue processors. 115-118
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