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ORCIDReCoSoC 2013: Darmstadt, Germany
- 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), Darmstadt, Germany, July 10-12, 2013. IEEE 2013, ISBN 978-1-4673-6180-4
- Shuo Li, Ahmed Hemani:
Memory allocation and optimization in system-level architectural synthesis. 1-7 - Juan Carlos Pena Ramos, Marian Verhelst
:
Flexible, ultra-low power sensor nodes through configurable finite state machines. 1-7 - Christoph Roth, Harald Bucher, Simon Reder, Oliver Sander, Jürgen Becker:
Improving parallel MPSoC simulation performance by exploiting dynamic routing delay prediction. 1-8 - Eduardo Cuevas-Farfan, Miguel Morales-Sandoval, René Cumplido, Claudia Feregrino-Uribe, Ignacio Algredo-Badillo:
A programmable FPGA-based cryptoprocessor for bilinear pairings over F2m. 1-8 - Juan M. Campos, René Cumplido, Claudia Feregrino-Uribe, Roberto Perez-Andrade:
A parallelization methodology for reconfigurable systems applied to edge detection. 1-7 - Martin Kumm, Konrad Möller, Peter Zipf:
Dynamically reconfigurable FIR filter architectures with fast reconfiguration. 1-8 - Simen Gimle Hansen, Dirk Koch, Jim Tørresen:
Simulation framework for cycle-accurate RTL modeling of partial run-time reconfiguration in VHDL. 1-8 - Maicon A. Sartin, Alexandre C. R. da Silva:
Approximation of hyperbolic tangent activation function using hybrid methods. 1-6 - Matthias Hiller, Georg Sigl, Michael Pehl:
A new model for estimating bit error probabilities of Ring-Oscillator PUFs. 1-8 - Francesco Robino, Johnny Öberg:
The HeartBeat model: A platform abstraction enabling fast prototyping of real-time applications on NoC-based MPSoC on FPGA. 1-8 - Juan Fernando Eusse, Christopher Williams, Rainer Leupers:
CoEx: A novel profiling-based algorithm/architecture co-exploration for ASIP design. 1-8 - Christian Stüllein, Norbert Abel, Udo Kebschull:
Bitfile preservation - Generation of reusable out of context modules. 1-6 - Jesús Carabaño, Francisco Dios, Masoud Daneshtalab, Masoumeh Ebrahimi:
An exploration of heterogeneous systems. 1-7 - Alexander Wold, Dirk Koch, Jim Tørresen:
Component based design using constraint programming for module placement on FPGAs. 1-8 - Marco Ramírez, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila:
Towards a Configurable Many-core Accelerator for FPGA-based embedded systems. 1-4 - Gerald Hempel, Jan Hoyer, Thilo Pionteck, Christian Hochberger:
Register allocation for high-level synthesis of hardware accelerators targeting FPGAs. 1-6 - Fabio Cancare, Christian Pilato, Andrea Cazzaniga, Donatella Sciuto, Marco D. Santambrogio:
D-RECS: A complete methodology to implement Self Dynamic Reconfigurable FPGA-based systems. 1-6 - Bernhard Jungk, Marc Stöttinger:
Among slow dwarfs and fast giants: A systematic design space exploration of KECCAK. 1-8 - Riccardo Cattaneo, Xinyu Niu, Christian Pilato, Tobias Becker, Wayne Luk, Marco D. Santambrogio:
A framework for effective exploitation of partial reconfiguration in dataflow computing. 1-8 - James Harbin, Leandro Soares Indrusiak:
Dynamic task remapping for power and latency performance improvement in priority-based non-preemptive Networks On Chip. 1-7 - Alexander Logvinenko, Carsten Gremzow, Dietmar Tutsch:
RecMIN: A reconfiguration architecture for network on chip. 1-6 - Philipp Gorski, Dirk Timmermann:
Centralized traffic monitoring for online-resizable clusters in Networks-on-Chip. 1-8 - Vianney Lapotre, Michael Hübner, Guy Gogniat, Purushotham Murugappa, Amer Baghdadi, Jean-Philippe Diguet:
An efficient on-chip configuration infrastructure for a flexible multi-ASIP turbo decoder architecture. 1-8 - Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
An FPGA design and implementation framework combined with commercial VLSI CADs. 1-7 - Jörg Walter, Jörg Lenhardt, Wolfram Schiffmann:
SoC performance evaluation with ArchC and TLM-2.0. 1-8 - Ingrid Exurville, Jacques J. A. Fournier, Jean-Max Dutertre, Bruno Robisson, Assia Tria:
Practical measurements of data path delays for IP authentication & integrity verification. 1-6 - Kartikeya Bhardwaj, Pravin S. Mane:
ACMA: Accuracy-configurable multiplier architecture for error-resilient System-on-Chip. 1-6 - Daniela Genius:
Measuring memory access latency for software objects in a NUMA system-on-chip architecture. 1-8 - André Himmighofen, Bernhard Jungk, Steffen Reith:
On a FPGA-based method for authentication using Edwards curves. 1-7 - Jens Huthmann, Björn Liebig, Julian Oppermann, Andreas Koch:
Hardware/software co-compilation with the Nymble system. 1-8 - Bouthaina Damak, Mouna Baklouti, Smaïl Niar, Mohamed Abid:
Shared hardware accelerator architectures for heterogeneous MPSoCs. 1-6 - Michael Dreschmann, Oliver Sander, Alexander Klimm, Christoph Roth, Jürgen Becker:
Addiguration: Exploring configuration behavior of Spartan-3 devices. 1-6 - Dominic Hillenbrand, Yuuki Furuyama, Akihiro Hayashi, Hiroki Mikami, Keiji Kimura, Hironori Kasahara:
Reconciling application power control and operating systems for optimal power and performance. 1-8 - Shivam Bhasin, Wei He, Sylvain Guilley, Jean-Luc Danger:
Exploiting FPGA block memories for protected cryptographic implementations. 1-8 - Anup Das, Amit Kumar Singh, Akash Kumar:
Energy-aware dynamic reconfiguration of communication-centric applications for reliable MPSoCs. 1-7
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