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ORCIDReConFig 2013: Cancun, Quintana Roo, Mexico
- 2012 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2013, Cancun, Mexico, December 9-11, 2013. IEEE 2013, ISBN 978-1-4799-2079-2
- Timm Bostelmann, Sergei Sawitzki:
Improving FPGA placement with a self-organizing map. 1-6 - Ren Chen, Viktor K. Prasanna:
Energy-efficient architecture for stride permutation on streaming data. 1-7 - Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez:
Lightweight and compact solutions for secure reconfiguration of FPGAs. 1-4 - B. I. Gea-Garcia, J. L. Vázquez-Avila, Remberto Sandoval-Arechiga, J. L. Pizano-Escalante, Ramón Parra-Michel, Mario Siller:
NoC-based hardware function libraries for running multiple DSP algorithms. 1-6 - Yann Thoma, Alberto Dassatti
, Daniel Molla:
FPGA2: An open source framework for FPGA-GPU PCIe communication. 1-6 - Muhammed Al Kadi, Patrick Rudolph, Diana Göhringer, Michael Hübner:
Dynamic and partial reconfiguration of Zynq 7000 under Linux. 1-5 - Kiran Kumar Matam, Viktor K. Prasanna:
Energy-efficient large-scale matrix multiplication on FPGAs. 1-8 - Swamy D. Ponpandi, Zhang Zhang, Akhilesh Tyagi:
PolyNOC - A polymorphic thread simulator for NoC communication based embedded systems. 1-8 - Luis F. Gonzalez-Perez, Lennin C. Yllescas-Calderon, Ramón Parra-Michel:
Parallel and configurable turbo decoder implementation for 3GPP-LTE. 1-6 - Edgar Mora-Sanchez, Jason Helge Anderson:
Leakage power reduction in FPGA DSP circuits through algorithmic noise tolerance. 1-6 - Yu Wang, Hyunchul Shin:
An effective window based legalization algorithm for FPGA placement. 1-4 - Keisuke Dohi, Kota Fukumoto, Yuichiro Shibata, Kiyoshi Oguri:
Performance modeling and optimization of 3-D stencil computation on a stream-based FPGA accelerator. 1-6 - Elif Bilge Kavun, Gregor Leander, Tolga Yalçin:
A reconfigurable architecture for searching optimal software code to implement block cipher permutation matrices. 1-8 - Omar Ahmed, Shawki Areibi:
An efficient application-specific instruction-set processor for packet classification. 1-6 - Markus Weinhardt, Alexander Krieger, Thomas Kinder:
A framework for PC applications with portable and scalable FPGA accelerators. 1-6 - Angel Gallego, Javier Mora, Andrés Otero, Eduardo de la Torre, Teresa Riesgo:
A scalable evolvable hardware processing array. 1-7 - Maya B. Gokhale:
Keynote 3 - Extreme scale challenges: Can reconfigurable computing come to the rescue? 1 - Marco Antonio Soto Hernandez, Oscar Alvarado Nava, Eduardo Rodriguez-Martinez, Francisco Javier Zaragoza Martínez:
Tree-less Huffman coding algorithm for embedded systems. 1-6 - Luis Manuel Ledesma-Carrillo, Misael Lopez-Ramirez, Ana L. Martinez-Herrera:
FPGA-based reconfigurable unit for image filtering in frequency domain. 1-6 - Swapnil Haria, Viktor K. Prasanna:
Optimal mapping of multiple packet lookup schemes onto FPGA. 1-8 - Remi Chaintreuil, Rie Uno, Hideharu Amano:
MCMA: A modular processing elements array based low-power coarse-grained reconfigurable accelerator. 1-6 - Chuan Shan, Eldar Zianbetov, Weiqiang Yu, François Anceau, Olivier Billoint, Dimitri Galayko:
FPGA prototyping of large reconfigurable ADPLL network for distributed clock generation. 1-6 - Roberto Ammendola, Andrea Biagioni, Ottorino Frezza, Francesca Lo Cicero, Alessandro Lonardo, Pier Stanislao Paolucci, Davide Rossetti, Francesco Simula, Laura Tosoratto, Piero Vicini:
Design and implementation of a modular, low latency, fault-aware, FPGA-based network interface. 1-6 - Joshua S. Monson, Michael J. Wirthlin, Brad L. Hutchings:
Optimization techniques for a high level synthesis implementation of the Sobel filter. 1-6 - Jean-Pierre David:
Max-hashing fragments for large data sets detection. 1-6 - Poona Bahrebar, Dirk Stroobandt:
The Hamiltonian-based odd-even turn model for adaptive routing in interconnection networks. 1-6 - Aydin Aysu, Patrick Schaumont:
PASC: Physically authenticated stable-clocked soc platform on low-cost FPGAs. 1-6 - Kevin Zeng, Peter Athanas:
Enhancing productivity with back-end similarity matching of digital circuits for IP reuse. 1-6 - Milica Orlandic, Kjetil Svarstad:
A low complexity H.264/AVC 4×4 intra prediction architecture with macroblock/block reordering. 1-6 - Paolo Maistri, Sébastien Tiran, Philippe Maurine, Israel Koren, Régis Leveugle:
Countermeasures against EM analysis for a secured FPGA-based AES implementation. 1-6 - Krishna K. Nagar, Jason D. Bakos:
Accuracy, cost, and performance tradeoffs for floating-point accumulation. 1-4 - Abdulhadi Shoufan:
A fault attack on a hardware-based implementation of the secure hash algorithm SHA-512. 1-7 - Vinod Pangracious, Habib Mehrez, Nizar Beltaief, Zied Marrakchi, Umer Farooq:
Exploration environment for 3D heterogeneous tree-based FPGA architectures (3D HT-FPGA). 1-6 - Duarte Lopes de Oliveira, Diego Bompean, Lester de Abreu Faria, Joao Luis V. Oliveira:
Design of asynchronous systems on FPGA using direct mapping and synchronous specification. 1-6 - Alberto Rodriguez-Garcia, Luis Pizano-Escalante, Ramón Parra-Michel, Omar Humberto Longoria-Gandara, Joaquín Cortez González:
Fast fixed-point divider based on Newton-Raphson method and piecewise polynomial approximation. 1-6 - Victor Dumitriu, Lev Kirischian:
SoC self-integration mechanism for dynamic reconfigurable systems based on collaborative macro-function units. 1-7 - Kevin L. Thomas, Michael S. Thompson:
Performance modeling of reconfigurable distributed systems based on the opensparc FPGA board and the SIRC communication framework. 1-7 - Sam Skalicky, Christopher A. Wood, Marcin Lukowiak, Matthew Ryan:
High level synthesis: Where are we? A case study on matrix multiplication. 1-7 - Horácio C. Neto, Mário P. Véstias:
Very low resource table-based FPGA evaluation of elementary functions. 1-6 - Garbi Singla, Félix Tobajas, Valentin de Armas:
Video super resolution algorithm implemented on a low-cost NoC-based MPSoC platform. 1-6 - Thomas Schweizer, Wolfgang Rosenstiel, Luigi Vaz Ferreira, Marcus Ritt:
Timing error handling on CGRAs. 1-6 - Jun Rong Wang, Dan Wang, Jin-Mei Lai:
A hierarchical parallel evolvable hardware based on network on chip. 1-6 - Tim Gallagher:
Keynote 2 - Past, current, and future of faster, cheaper, better. 1 - Yu Bai, Mohammed Alawad, Michael Riera, Mingjie Lin:
Improving memory performance in reconfigurable computing architecture through hardware-assisted dynamic graph. 1-8 - Andrea Sanny, Viktor K. Prasanna:
Energy-efficient Median filter on FPGA. 1-8 - Juan Carlos Moctezuma, Joseph McGeehan, José Luis Núñez-Yáñez:
Numerically efficient and biophysically accurate neuroprocessing platform. 1-6 - Bryant C. Lam, Carlo Pascoe, Scott Schaecher, Herman Lam, Alan D. George:
BSW: FPGA-accelerated BLAST-Wrapped Smith-Waterman aligner. 1-7 - Jo Vliegen, Nele Mentens, Ingrid Verbauwhede:
A single-chip solution for the secure remote configuration of FPGAs using bitstream compression. 1-6 - Moritz Schmid, Markus Blocherer, Frank Hannig, Jürgen Teich:
Real-timerange image preprocessing on FPGAs. 1-8 - Takeshi Hirao, Dahoo Kim, Itaru Hida, Tetsuya Asai, Masato Motomura:
A restricted dynamically reconfigurable architecture for low power processors. 1-7 - Michael Rückauer, Daniel M. Muñoz, Timo Stripf, Oliver Oey, Carlos H. Llanos, Jürgen Becker:
A flexible implementation of the PSO algorithm for fine- and coarse-grained reconfigurable embedded systems. 1-6 - Jahanzeb Anwer, Sebastian Meisner, Marco Platzner:
Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime. 1-6 - Da Tong, Viktor K. Prasanna:
Online heavy hitter detector on FPGA. 1-6 - Milovan Duric, Oscar Palomar, Aaron Smith:
ReCompAc: Reconfigurable compute accelerator. 1-4 - Ali Ebrahim, Khaled Benkrid, Jalal Khalifat, Chuan Hong:
A platform for secure IP integration in Xilinx Virtex FPGAs. 1-6 - Pedro Cervantes Lozano, Luis Fernando González Pérez, Andrés David García García:
A VLSI architecture for the QR decomposition based on the MCGR algorithm. 1-6 - Durga Prasad Sahoo, Debdeep Mukhopadhyay, Rajat Subhra Chakraborty:
Design of low area-overhead ring oscillator PUF with large challenge space. 1-6 - Emna Amouri, Adrien Blanchardon, Roselyne Chotin-Avot, Habib Mehrez, Zied Marrakchi:
Efficient multilevel interconnect topology for cluster-based mesh FPGA architecture. 1-6 - Jan Heisswolf, Maximilian Singh, Martin Kupper, Ralf König, Jürgen Becker:
Rerouting: Scalable NoC self-optimization by distributed hardware-based connection reallocation. 1-8 - Steve Trimberger:
Keynote 1 - Moore's law, programmable logic and reconfigurable systems. 1 - Guillaume Reymond, Victor Murillo:
A hardware pipelined architecture of a scalable Montgomery modular multiplier over GF(2m). 1-6 - Michal Varchola, Milos Drutarovský, Viktor Fischer:
New universal element with integrated PUF and TRNG capability. 1-6 - Zoltán Endre Rákossy, Axel Acosta-Aponte, Anupam Chattopadhyay:
Exploiting architecture description language for diverse IP synthesis in heterogeneous MPSoC. 1-6 - Sam Skalicky, Sonia López, Marcin Lukowiak:
Distributed execution of transmural electrophysiological imaging with CPU, GPU, and FPGA. 1-7 - Byron Navas, Johnny Öberg, Ingo Sander:
Towards the generic reconfigurable accelerator: Algorithm development, core design, and performance analysis. 1-6 - Cristina I. Muresan, George Dan Mois, Silviu Folea, Clara M. Ionescu:
Alternative implementations of a fractional order control algorithm on FPGAs. 1-6 - Oguzhan Erdem, Aydin Carus:
Range tree-linked list hierarchical search structure for packet classification on FPGAs. 1-6 - Raymond J. Weber, Justin A. Hogan, Brock J. LaMeres:
Power efficiency benchmarking of a partially reconfigurable, many-tile system implemented on a Xilinx Virtex-6 FPGA. 1-4 - Roberto Perez-Andrade, César Torres-Huitzil, René Cumplido, Juan M. Campos:
Processor arrays generation for matrix algorithms used in embedded platforms. 1-6 - Matthias Hinkfoth, Ralf Joost, Ralf Salomon:
Improving calibration precision of signal-delay-based time measurement systems in FPGAs. 1-6 - Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Hiroyuki Ochi, Takashi Imagawa, Shinichi Noda, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye:
Mixed-grained reconfigurable architecture supporting flexible reliability and C-based design. 1-6 - Salvador Ibarra-Delgado, Manuel Hernandez Calviño, Nicolás Guil Mata, Juan Gómez-Luna:
A robust and low resource FPGA-based stereoscopic vision algorithm. 1-6 - Hamed Sajjadi Kia, Mohammad A. Zare, Rajesh G. Kavasseri, Cristinel Ababei:
Dynamic simulation of direct torque control of induction motors with FPGA based accelerators. 1-6 - Mingjie Lin, Shaoyi Cheng, John Wawrzynek:
Extracting memory-level parallelism through reconfigurable hardware traces. 1-8 - Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez:
Improved method for parallel AES-GCM cores using FPGAs. 1-4 - Umer I. Cheema, Ashfaq A. Khokhar:
A high performance architecture for computing burrows-wheeler transform on FPGAs. 1-6 - Gary Plumbridge, Neil C. Audsley:
Programming FPGA based NoCs with Java. 1-6 - Fabian May, Friedrich Mayer-Lindenberg:
ModHDL: A modular and expandable language for developing synchronous hardware. 1-6 - Qingyu Liu, Yuchun Ma, Yu Wang, Wayne Luk, Jinian Bian:
RALP: Reconvergence-aware layer partitioning for 3D FPGAs. 1-6 - Mohamed Ben Jrad, Régis Leveugle:
Automated design flow for no-cost configuration error detection in sram-based FPGAs. 1-6 - Miaoqing Huang, Shiming Li:
A delay-based PUF design using multiplexer chains. 1-6 - Christian de Schryver, Philipp Schläfer, Norbert Wehn, Thomas Fischer, Arnd Poetzsch-Heffter:
Loopy - An open-source TCP/IP rapid prototyping and validation framework. 1-6 - Jonas Gomes Filho, Jiang Chau Wang:
Exploring the problems of placement and mapping in NoC-based reconfizurable systems. 1-4
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