default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDReConFig 2009: Cancun, Quintana Roo, Mexico
- Viktor K. Prasanna, Lionel Torres, René Cumplido:
ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, Cancun, Quintana Roo, Mexico, 9-11 December 2009, Proceedings. IEEE Computer Society 2009, ISBN 978-0-7695-3917-1
General Sessions
- Lei Wang, Lei Chen, Zhiping Wen, Huabo Sun, Shuo Wang:
A Novel High-Density Single-Event Upset Hardened Configurable SRAM Applied to FPGA. 1-5 - Malte Baesler, Thomas Teufel:
FPGA Implementation of a Decimal Floating-Point Accurate Scalar Product Unit with a Parallel Fixed-Point Multiplier. 6-11 - Sven Eisenhardt, Thomas Schweizer, Andreas Bernauer, Tommy Kuhn, Wolfgang Rosenstiel:
Prevention of Hot Spot Development on Coarse-Grained Dynamically Reconfigurable Architectures. 12-17 - Yoann Guillemenet, Syed Zahid Ahmed, Lionel Torres, Alexandre Martheley, Julien Eydoux, Jean-Baptiste Cuelle, Laurent Rouge, Gilles Sassatelli:
MRAM Based eFPGAs: Programming and Silicon Flows, Exploration Environments, MRAM Current State in Industry and Its Unique Potentials for FPGAs. 18-23 - Taciano A. Rodolfo
, Ney Laert Vilar Calazans, Fernando Gehm Moraes:
Floating Point Hardware for Embedded Processors in FPGAs: Design Space Exploration for Performance and Area. 24-29 - Guilherme Montez Guindani, Frederico Ferlini, Jeferson Oliveira, Ney Laert Vilar Calazans, Daniel V. Pigatto, Fernando Gehm Moraes:
A 10 Gbps OTN Framer Implementation Targeting FPGA Devices. 30-35 - Gustavo Sutter, Elias Todorovich, Gery Bioul, Martín Vázquez, Jean-Pierre Deschamps:
FPGA Implementations of BCD Multipliers. 36-41 - Martín Vázquez, Gustavo Sutter, Gery Bioul, Jean-Pierre Deschamps:
Decimal Adders/Subtractors in FPGA: Efficient 6-input LUT Implementations. 42-47 - Jiang Jiang, Vincent Mirian, Kam Pui Tang, Paul Chow, Zuocheng Xing:
Matrix Multiplication Based on Scalable Macro-Pipelined FPGA Accelerator Architecture. 48-53 - Armando Astarloa, Jesús Lázaro, Unai Bidarte, Aitzol Zuloaga, Jaime Jimenez:
PCIREX: A Fast Prototyping Platform for TMR Dynamically Reconfigurable Systems. 54-58 - Carlos Minchola, Gustavo Sutter:
A FPGA IEEE-754-2008 Decimal64 Floating-Point Multiplier. 59-64 - Marcus Jeitler, Jakob Lechner:
Speeding up Fault Injection for Asynchronous Logic by FPGA-Based Emulation. 65-70 - Vlad Mihai Sima, Koen Bertels:
Runtime Memory Allocation in a Heterogeneous Reconfigurable Platform. 71-76 - Rafael A. Arce-Nazario, Edusmildo Orozco, Dorothy Bollman:
A Systolic Array Based Architecture for Implementing Multivariate Polynomial Interpolation Tasks. 77-82 - Alireza Rohani, Hamid R. Zarandi:
A New CLB Architecture for Tolerating SEU in SRAM-Based FPGAs. 83-88 - Adwait Gupte, Phillip H. Jones:
Hotspot Mitigation Using Dynamic Partial Reconfiguration for Improved Performance. 89-94 - Mingjie Lin, Yaling Ma:
Base-Calling in DNA Pyrosequencing with Reconfigurable Bayesian Network. 95-100
High Performance Reconfigurable Computing
- Eduardo Cabal-Yepez, Roque Alfredo Osornio-Rios, René de Jesús Romero-Troncoso, J. R. Razo-Hernandez, R. Lopez-Garcia:
FPGA-Based Online Induction Motor Multiple-Fault Detection with Fused FFT and Wavelet Analysis. 101-106 - Mathieu Allard, Patrick Grogan, Jean-Pierre David:
A Scalable Architecture for Multivariate Polynomial Evaluation on FPGA. 107-112 - Mondrian Nüssle, Benjamin Geib, Holger Fröning, Ulrich Brüning:
An FPGA-Based Custom High Performance Interconnection Network. 113-118 - Tobias Schumacher, Tim Süß, Christian Plessl, Marco Platzner:
Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000. 119-124 - Hideki Yamada, Yasunori Osana, Tomoya Ishimori, Tomonori Ooya, Masato Yoshimi, Yuri Nishikawa, Akira Funahashi, Noriko Hiroi, Hideharu Amano, Yuichiro Shibata, Kiyoshi Oguri:
A Modular Approach to Heterogeneous Biochemical Model Simulation on an FPGA. 125-130 - Siddhartha Datta, Ron Sass:
Scalability Studies of the BLASTn Scan and Ungapped Extension Functions. 131-136 - Abel G. Silva-Filho, Sidney M. L. Lima, F. C. L. Cox:
Low Power RTL Exploration Mechanism Based on the Cache Parameters. 137-142 - James Coole, John Robert Wernsing, Greg Stitt:
A Traversal Cache Framework for FPGA Acceleration of Pointer Data Structures: A Case Study on Barnes-Hut N-body Simulation. 143-148 - Guillermo Conde, Gregory W. Donohoe, Siva Maheswaran:
Low Power, Reconfigurable Computing Platform for Spacecraft. 149-154 - Naoki Tanida, Mary Inaba, Kei Hiraki, Takeshi Yoshino:
Hardware Accelerator for Full-Text Search (HAFTS) with Succinct Data Structure. 155-160 - Kenichi Koizumi, Mary Inaba, Kei Hiraki, Yasuo Ishii, Takefumi Miyoshi, Kazuki Yoshizoe:
Triple Line-Based Playout for Go - An Accelerator for Monte Carlo Go. 161-166 - Oscar Alvarado Nava, Arturo Díaz-Pérez:
Acceleration of Fractal Image Compression Using the Hardware-Software Co-design Methodology. 167-171 - Sergio Ruben Geninatti, José Ignacio Benavides Benítez, Manuel Hernandez Calviño, Nicolás Guil Mata, Juan Gómez-Luna:
FPGA Implementation of the Generalized Hough Transform. 172-177 - Çaglar Yilmaz, Mustafa Gök:
An Optimized System for Multiple Sequence Alignment. 178-182
Reconfigurable Computing for Security and Cryptography
- Julien Bringer, Hervé Chabanne, Jean-Luc Danger:
Protecting the NOEKEON Cipher against SCARE Attacks in FPGAs by Using Dynamic Implementations. 183-188 - Stephanie Drzevitzky, Uwe Kastens, Marco Platzner:
Proof-Carrying Hardware: Towards Runtime Verification of Reconfigurable Modules. 189-194 - Marcio Juliato, Catherine H. Gebotys:
Tailoring a Reconfigurable Platform to SHA-256 and HMAC through Custom Instructions and Peripherals. 195-200 - Emna Amouri, Hayder Mrabet, Zied Marrakchi, Habib Mehrez:
Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing. 201-206 - Ahmet Onur Durahim, Erkay Savas, Kazim Yumbul:
Implementing a Protected Zone in a Reconfigurable Processor for Isolated Execution of Cryptographic Algorithms. 207-212 - Shivam Bhasin, Jean-Luc Danger, Florent Flament, Tarik Graba, Sylvain Guilley, Yves Mathieu, Maxime Nassar, Laurent Sauvage, Nidhal Selmane:
Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow. 213-218 - Solmaz Ghaznavi, Catherine H. Gebotys, Reouven Elbaz:
Efficient Technique for the FPGA Implementation of the AES MixColumns Transformation. 219-224 - Panasayya Yalla, Jens-Peter Kaps:
Lightweight Cryptography for FPGAs. 225-230 - Antoine Trouvé, Lovic Gauthier, Takayuki Kando, Benoit Ryder, Sebastien Pouzols, Pradeep Rao, Norifumi Yoshimatsu, Kazuaki J. Murakami:
Accelerating Cryptographic Applications Using Dynamically Reconfigurable Functional Units. 231-236 - Nathalie Bochard, Florent Bernard, Viktor Fischer:
Observing the Randomness in RO-Based TRNG. 237-242 - Laurent Sauvage, Maxime Nassar, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu:
DPL on Stratix II FPGA: What to Expect?. 243-248 - Mark Hamilton, William P. Marnane:
FPGA Implementation of an Elliptic Curve Processor Using the GLV Method. 249-254 - Brian Baldwin, William P. Marnane, Robert Granger:
Reconfigurable Hardware Implementation of Arithmetic Modulo Minimal Redundancy Cyclotomic Primes for ECC. 255-260 - Johann Großschädl, Erkay Savas, Kazim Yumbul:
Realizing Arbitrary-Precision Modular Multiplication with a Fixed-Precision Multiplier Datapath. 261-266
Multiprocessor Systems and Networks on Chip
- Vitor de Paulo, Cristinel Ababei:
A Framework for 2.5D NoC Exploration Using Homogeneous Networks over Heterogeneous Floorplans. 267-272 - Taho Dorta, Jaime Jimenez, José Luis Martín, Unai Bidarte, Armando Astarloa:
Overview of FPGA-Based Multiprocessor Systems. 273-278 - Pablo Huerta, Javier Castillo, César Pedraza, Javier Cano, José Ignacio Martínez:
Symmetric Multiprocessor Systems on FPGA. 279-283 - Hung-Manh Pham, Sébastien Pillement, Didier Demigny:
A Fault-Tolerant Layer for Dynamically Reconfigurable Multi-processor System-on-Chip. 284-289 - Arghavan Asad, Amir Ehsani Zonouz, Mehrdad Seyrafi, Mohsen Soryani, Mahmood Fathy:
Modeling and Analyzing of Blocking Time Effects on Power Consumption in Network-on-Chips. 290-295 - Rachid Dafali, Jean-Philippe Diguet:
Self-Adaptive Network Interface (SANI): Local Component of a NoC Configuration Manager. 296-301 - Fritz Mayer-Lindenberg:
High-Level FPGA Programming through Mapping Process Networks to FPGA Resources. 302-307
Reconfigurable Computing for DSP and Communications
- Leonard Colavito, Dennis Silage:
Efficient PGA LFSR Implementation Whitens Pseudorandom Numbers. 308-313 - Leonard Colavito, Dennis Silage:
Composite Look-Up Table Gaussian Pseudo-Random Number Generator. 314-319 - Hector Borrayo-Sandoval, Ramón Parra-Michel, Luis F. Gonzalez-Perez, Fernando Landeros Printzen, Claudia Feregrino-Uribe:
Design and Implementation of a Configurable Interleaver/Deinterleaver for Turbo Codes in 3GPP Standard. 320-325 - Mark E. Dunham, Zachary K. Baker, Matthew Stettler, Michael Pigue, Paul S. Graham, Eric N. Schmierer, John Power:
High Efficiency Space-Based Software Radio Architectures: A Minimum Size, Weight, and Power TeraOps Processor. 326-331 - Daniel Llamocca, Marios S. Pattichis, G. Alonzo Vera:
A Dynamically Reconfigurable Platform for Fixed-Point FIR Filters. 332-337 - Chenxin Zhang, Thomas Lenart, Henrik Svensson, Viktor Öwall:
Design of Coarse-Grained Dynamically Reconfigurable Architecture for DSP Applications. 338-343 - Asadollah Shahbahrami, Mahmood Ahmadi, Stephan Wong, Koen Bertels:
A New Approach to Implement Discrete Wavelet Transform Using Collaboration of Reconfigurable Elements. 344-349 - Jorge Surís, Adolfo Recio, Peter Athanas:
Enhancing the Productivity of Radio Designers with RapidRadio. 350-355 - Juan Fernando Eusse Giraldo, Ricardo Pezzuol Jacobi:
Signal Processing Domain Application Mapping on the Brick Reconfigurable Array. 356-361
Reconfigurable Techniques
- Laurent Gantel, Salah Layouni, Mohamed El Amine Benkhelifa, François Verdier, Stéphanie Chauvet:
Multiprocessor Task Migration Implementation in a Reconfigurable Platform. 362-367 - Lev Kirischian, Victor Dumitriu, Pil Woo Chun:
Virtualization of Computing Resources in RCS for Multi-task Stream Applications. 368-373 - Abelardo Jara-Berrocal, Ann Gordon-Ross:
Runtime Temporal Partitioning Assembly to Reduce FPGA Reconfiguration Time. 374-379 - Muhammad Aqeel Wahlah, Kees Goossens:
Composable and Persistent-State Application Swapping on FPGAs Using Hardwired Network on Chip. 380-385 - Julien Delorme, Amor Nafkha, Pierre Leray, Christophe Moy:
New OPBHWICAP Interface for Realtime Partial Reconfiguration of FPGA. 386-391 - Jochen Strunk, Toni Volkmer, Wolfgang Rehm, Heiko Schick:
Design and Performance of a Grid of Asynchronously Clocked Run-Time Reconfigurable Modules on a FPGA. 392-397
Reconfigurable Computing for Robotics
- Mark G. Arnold, Jung H. Cho:
Parallax-Docking and Reconfiguration of Field Programmable Robot Arrays Using an Intermittently-Powered One-Hot Controller. 398-403 - John A. Kalomiros, John N. Lygouras:
A Reconfigurable Architecture for Stereo-Assisted Detection of Point-Features for Robot Mapping. 404-409 - C. Yesid E. Castro, Carlos H. Llanos, Walter de Britto Vidal Filho, Leandro dos Santos Coelho:
Fuzzy Control for Cyclist Robot Stability Using FPGAs. 410-415 - Diego F. Sánchez, Daniel M. Muñoz, Carlos H. Llanos, Jose M. Motta:
FPGA Implementation for Direct Kinematics of a Spherical Robot Manipulator. 416-421 - César Torres-Huitzil:
On the Implementation of Central Pattern Generators for Periodic Rhythmic Locomotion. 422-426
Bioinspired and Self-Adaptive Computing
- André Stauffer, Joël Rossier:
Bio-inspired Self-Testing and Self-Organizing Bit Slice Processors. 427-432 - Stefan Döbrich, Christian Hochberger:
Effects of Simplistic Online Synthesis for AMIDAR Processors. 433-438 - Ming Liu, Zhonghai Lu, Wolfgang Kuehn, Shuo Yang, Axel Jantsch:
A Reconfigurable Design Framework for FPGA Adaptive Computing. 439-444 - Javier Soto Vargas, Juan Manuel Moreno, Jordi Madrenas, Joan Cabestany:
Implementation of a Dynamic Fault-Tolerance Scaling Technique on a Self-Adaptive Hardware Architecture. 445-450 - Kenneth L. Rice, Mohammad Ashraf Bhuiyan, Tarek M. Taha, Christopher N. Vutsinas, Melissa C. Smith:
FPGA Implementation of Izhikevich Spiking Neural Networks for Character Recognition. 451-456
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2026-04-30 23:07 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
