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ORCID22nd PATMOS 2012: Newcastle upon Tyne, UK
- José L. Ayala, Delong Shang, Alex Yakovlev:
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 22nd International Workshop, PATMOS 2012, Newcastle upon Tyne, UK, September 4-6, 2012, Revised Selected Papers. Lecture Notes in Computer Science 7606, Springer 2013, ISBN 978-3-642-36156-2 - Sven Rosinger, Wolfgang Nebel:
Sleep-Transistor Based Power-Gating Tradeoff Analyses. 1-10 - Chenxi Ni, Ziyad Al Tarawneh, Gordon Russell, Alexandre V. Bystrov
:
Modelling and Analysis of Manufacturing Variability Effects from Process to Architectural Level. 11-20 - Daniel Lorenz, Philipp A. Hartmann, Kim Grüttner, Wolfgang Nebel:
Non-invasive Power Simulation at System-Level with SystemC. 21-31 - Masahiro Kondo, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera:
A Standard Cell Optimization Method for Near-Threshold Voltage Operations. 32-41 - Salomon Beer, Ran Ginosar:
An Extended Metastability Simulation Method for Synchronizer Characterization. 42-51 - Reef Eilers, Malte Metzdorf, Sven Rosinger, Domenik Helms, Wolfgang Nebel:
Phase Space Based NBTI Model. 52-61 - Axel Reimer, Lars Kosmann, Daniel Lorenz, Wolfgang Nebel:
Fast Propagation of Hamming and Signal Distances for Register-Transfer Level Datapaths. 62-71 - Tobias Gemmeke, Maryam Ashouei, Tobias G. Noll:
Noise Margin Based Library Optimization Considering Variability in Sub-threshold. 72-82 - Eyal-Itzhak Nave, Ran Ginosar:
TCP Window Based DVFS for Low Power Network Controller SoC. 83-92 - Ghaith Tarawneh, Alex Yakovlev:
Adaptive Synchronization for DVFS Applications. 93-102 - Thomas Polzer, Andreas Steininger, Jakob Lechner:
Muller C-Element Metastability Containment. 103-112 - José Miguel Mora-Gutierrez, Carlos Jesús Jiménez-Fernández, Manuel Valencia-Barrero:
Low Power Implementation of Trivium Stream Cipher. 113-120 - Jakob Lechner, Robert Najvirt:
A Generic Architecture for Robust Asynchronous Communication Links. 121-130 - Javier Rodríguez, Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs:
Direct Statistical Simulation of Timing Properties in Sequential Circuits. 131-141 - Jordi Perez-Puigdemont, Antonio Calomarde, Francesc Moll:
PVTA Tolerant Self-adaptive Clock Generation Architecture. 142-154 - Hossein Karimiyan Alidash, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino:
On-Chip NBTI and PBTI Tracking through an All-Digital Aging Monitor Architecture. 155-165 - Juan Núñez, Maria J. Avedillo, José M. Quintana:
Two-Phase MOBILE Interconnection Schemes for Ultra-Grain Pipeline Applications. 166-174 - Pieter Weckx, Nele Reynders, Ilse de Moffarts, Wim Dehaene:
Design of a 150 mV Supply, 2 MIPS, 90nm CMOS, Ultra-Low-Power Microprocessor. 175-184 - Dimitris Bekiaris, Ioannis Kosmadakis, George I. Stassinopoulos, Dimitrios Soudris, Theodore Laopoulos, Gregory Doumenis, Stylianos Siskos:
Run-Time Measurement of Harvested Energy for Autarkic Sensor Operation. 185-193 - Panagiotis Sakellariou, Vassilis Paliouras:
Low-Power Delay Sensors on FPGAs. 194-204 - Arash Saifhashemi, Peter A. Beerel:
Observability Conditions and Automatic Operand-Isolation in High-Throughput Asynchronous Pipelines. 205-214 - Maryam Triki, Yanzhi Wang, Ahmed Chiheb Ammari, Massoud Pedram:
Dynamic Power Management of a Computer with Self Power-Managed Components. 215-224 - Jorge Juan, Julian Viejo, Manuel J. Bellido:
Network Time Synchronization: A Full Hardware Approach. 225-234 - Peng Li, Weikang Qian, David J. Lilja, Kia Bazargan, Marc D. Riedel:
Case Studies of Logical Computation on Stochastic Bit Streams. 235-244 - Jatin N. Mistry, John Biggs, James Myers, Bashir M. Al-Hashimi, David Flynn:
dRail: A Novel Physical Layout Methodology for Power Gated Circuits. 245-255
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