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MEDEA@PACT 2006: Seattle, WA, USA

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Proceedings of the 2006 workshop on MEmory performance - DEaling with Applications, systems and architectures, MEDEA '06, Seattle, Washington, USA, September 16-20, 2006. ACM 2006
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  - conf/medea/LortonW06
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K. Patrick Lorton, David S. Wise:
Analyzing block locality in Morton-order and Morton-hybrid matrices. 5-12
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Kaveh Jokar Deris, Amirali Baniasadi:
Investigating cache energy and latency break-even points in high performance processors. 13-20
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Jun Yan, Wei Zhang:
Evaluating instruction cache vulnerability to transient errors. 21-28
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  - conf/medea/RamirezPSV06
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Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero:
A simple speculative load control mechanism for energy saving. 29-36
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Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez, Víctor Viñals:
Data prefetching in a cache hierarchy with high bandwidth and capacity. 37-44
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  - conf/medea/DybdahlSN06
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Haakon Dybdahl, Per Stenström, Lasse Natvig:
An LRU-based replacement algorithm augmented with frequency of access in shared chip-multiprocessor caches. 45-52

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