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ORCIDLATW 2014: Fortaleza, Brazil
- 15th Latin American Test Workshop - LATW 2014, Fortaleza, Brazil, March 12-15, 2014. IEEE 2014
- Raimund Ubar
, Anton Tsertov, Artjom Jasnetski, Marina Brik:
Software-based self-test generation for microprocessors with high-level decision diagrams. 1-6 - Pablo Briff, Ariel Lutenberg, Leonardo Rey Vega, Fabian Vargas, Mohammad N. Patwary:
A novel control strategy for fail-safe cyclic data exchange in wireless sensor networks. 1-5 - Jose Luis Garcia-Gervacio, Jaime Martínez-Castillo, Víctor H. Champac:
Possibilities of defect-size magnification for testing resistive-opens in nanometer technologies. 1-6 - Omar Abdelmalek, David Hély, Vincent Beroulle:
Fault tolerance evaluation of RFID tags. 1-6 - Lucas A. Tambara, Jorge L. Tonfat, Ricardo Reis, Fernanda Lima Kastensmidt, Evaldo Carlos Fonseca Pereira, Rafael Galhardo Vaz, Odair Lelis Goncalez:
Soft error rate in SRAM-based FPGAs under neutron-induced and TID effects. 1-6 - Petr Pfeifer, Zdenek Plíva, Pieter Weckx, Ben Kaczer:
On reliability enhancement using adaptive core voltage scaling and variations on nanoscale FPGAs. 1-4 - Suraj Sindia, Vishwani D. Agrawal:
Specification test minimization for given defect level. 1-6 - S. Ben Krit, Wenceslas Rahajandraibe, Karine Castellani-Coulié, Gilles Micolau, Alexandre Levisse, A. Lyoussi:
Development of a digital tool for the simulation of a readout system dedicated for neutrons discrimination. 1-6 - Felipe Restrepo-Calle, Sergio Cuenca-Asensi, Antonio Martínez-Álvarez, Eduardo Chielle, Fernanda Lima Kastensmidt:
Efficient metric for register file criticality in processor-based systems. 1-6 - Syhem Larguech, Florence Azaïs, Serge Bernard, Vincent Kerzerho, Mariane Comte, Michel Renovell:
Evaluation of indirect measurement selection strategies in the context of analog/RF alternate testing. 1-6 - Carlos Ivan Castro Marquez, Marius Strum, Jiang Chau Wang:
A unified sequential equivalence checking approach to verify high-level functionality and protocol specification implementations in RTL designs. 1-6 - Salma Bergaoui, Pierre Vanhauwaert, Régis Leveugle:
IDSM: An improved disjoint signature monitoring scheme for processor behavioral checking. 1-6 - Shih-Yi Yuan:
Recent progress of software-related electromagnetic compatibility. 1-4 - Alan Carlos Junior Rossetto, Gilson Inácio Wirth, Ricardo Vanni Dallasen:
Performance analysis of a clock generator PLL under TID effects. 1-5 - Alisson J. C. Lanot, Tiago R. Balen:
Analysis of the effects of single event transients on an SAR-ADC based on charge redistribution. 1-5 - Werner Nedel, Fernanda Lima Kastensmidt, José Rodrigo Azambuja:
Implementation and experimental evaluation of a CUDA core under single event effects. 1-4 - Anna Vaskova, A. Fabregat, Marta Portela-García, Mario García-Valderas, Celia López-Ongil, Matteo Sonza Reorda:
Reducing SEU sensitivity in LIN networks: Selective and collaborative hardening techniques. 1-6 - Evaldo Carlos Fonseca Pereira, Odair Lelis Goncalez, Rafael Galhardo Vaz, Claudio Antonio Federico, Thiago Hanna Both, Gilson Inácio Wirth:
The effects of total ionizing dose on the neutron SEU cross section of a 130 nm 4 Mb SRAM memory. 1-4 - Filipe de Aguiar Geissler, Fernanda Lima Kastensmidt, Jose Eduardo Pereira Souza:
Soft error injection methodology based on QEMU software platform. 1-5 - Iuri A. C. Gomes, Mayler G. A. Martins, Fernanda Lima Kastensmidt, André Inácio Reis, Renato P. Ribas, Sylvain P. Novales:
Methodology for achieving best trade-off of area and fault masking coverage in ATMR. 1-6 - Cristiano P. Chenet, Alisson J. C. Lanot, Tiago R. Balen:
Design diversity redundancy with spatial-temporal voting applied to data acquisition systems. 1-6 - Karine Coulié-Castellani, Wenceslas Rahajandraibe, Gilles Micolau, Hassen Aziza, Jean-Michel Portal:
Improvement of a VCO concept for low energy particule detection and recognition. 1-4 - Hsun-Cheng Lee, Jacob A. Abraham:
Harmonic distortion correction for 8-bit delay line ADC using gray code. 1-4 - Nicola Bombieri, Franco Fummi, Valerio Guarnieri, Graziano Pravadelli, Francesco Stefanni, Tara Ghasempouri, Michele Lora, Giovanni Auditore, Mirella Negro Marcigaglia:
On the reuse of RTL assertions in SystemC TLM verification. 1-6 - Wassim Mansour, Pablo Ramos, Rafic A. Ayoubi, Raoul Velazco:
SEU fault-injection at system level: Method, tools and preliminary results. 1-5 - Stefan Weidling, Michael Gössel:
Fault tolerant linear state machines. 1-6 - Luca Piccolboni, Graziano Pravadelli:
Simplified stimuli generation for scenario and assertion based verification. 1-6 - Arwa Ben Dhia, Mariem Slimani, Lirida A. B. Naviner:
Improving the robustness of a switch box in a mesh of clusters FPGA. 1-6 - Jörg Behrend, Alexander Grünhage, Douglas Schroeder, Djones Lettnin, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel:
Optimized hybrid verification of embedded software. 1-6 - Sonia Ben Dhia, Alexandre Boyer:
Design of on-chip sensors to monitor electromagnetic activity in ICs: Towards on-line diagnosis and self-healing. 1-6 - Victor M. Goncalves Martins, Frederico Ferlini, Djones Vinicius Lettnin, Eduardo Augusto Bezerra:
Low cost fault detector guided by permanent faults at the end of FPGAs life cycle. 1-6 - Ricardo A. Guazzelli, Guilherme Heck, Matheus T. Moreira, Ney Laert Vilar Calazans:
Schmitt trigger on output inverters of NCL gates for soft error hardening: Is it enough? 1-5 - Sergei Kostin, Jaan Raik, Raimund Ubar, Maksim Jenihhin, Fabian Vargas, Letícia Maria Bolzani Poehls, Thiago Santos Copetti:
Hierarchical identification of NBTI-critical gates in nanoscale logic. 1-6
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