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ORCIDLATW 2012: Quito, Ecuador
- 13th Latin American Test Workshop, LATW 2012, Quito, Ecuador, April 10-13, 2012. IEEE Computer Society 2012, ISBN 978-1-4673-2355-0
- Alejandro Cook, Sybille Hellebrand, Michael E. Imhof, Abdullah Mumtaz, Hans-Joachim Wunderlich:
Built-in self-diagnosis targeting arbitrary defects with partial pseudo-exhaustive test. 1-4 - Walter E. Calienes Bartra
, Fernanda Lima Kastensmidt, Ricardo Reis:
Simulation of SET faults in a voltage controlled oscillator. 1-6 - Jesús Moreno, Víctor H. Champac, Michel Renovell:
Low voltage testing for interconnect opens under process variations. 1-6 - Kwanyeob Chae, Minki Cho, Saibal Mukhopadhyay:
Low-power design under variation using error prevention and error tolerance (invited paper). 1-6 - Jangjoon Lee, Srikar Bhagavatula, Kaushik Roy, Byunghoo Jung:
Variation-aware and self-healing design methodology for a system-on-chip. 1-4 - Hanno Hantson, Urmas Repinski, Jaan Raik, Maksim Jenihhin, Raimund Ubar:
Diagnosis and correction of multiple design errors using critical path tracing and mutation analysis. 1-6 - Alair Dias Junior, Diógenes Cecilio da Silva Júnior:
A guiding heuristic for the semi-formal verification of high-level designs. 1-6 - Alex R. Pinto, Adriano Mauro Cansian, José Marcio Machado, Carlos Montez:
Self-optimization of dense wireless sensor networks based on simulated annealing. 1-6 - Ahmed Amine Rekik, Florence Azaïs, Frédérick Mailly, Pascal Nouet:
Design-for-manufacturability of MEMS convective accelerometers through adaptive electrical calibration strategy. 1-6 - Arthur Ceratti, Thiago Copetti, Letícia Maria Veiras Bolzani, Fabian Vargas:
Investigating the use of an on-chip sensor to monitor NBTI effect in SRAM. 1-6 - Jose A. Rodriguez, Manuel Jiménez, William Morales, Fan-Chi Hou, Lucianne Millan, Rogelio Palomera:
Parametric DC and noise measurements in a unified test & characterization software tool framework. 1-6 - Rodolfo Adamshuk Silva, Simone do Rócio Senger de Souza, Paulo Sergio Lopes de Souza:
Mutation operators for concurrent programs in MPI. 1-6 - Jorge H. Meza Escobar, J. SachBe, Steffen Ostendorff, Heinz-Dietrich Wuttke:
Automatic generation of an FPGA based embedded test system for printed circuit board testing. 1-6 - Aleksandar Simevski, Rolf Kraemer, Milos Krstic:
Platform for automated HW/SW co-verification, testing and simulation of microprocessors. 1-5 - Raimund Ubar, Sergei Kostin, Jaan Raik:
About robustness of test patterns regarding multiple faults. 1-6 - Ivan Beretta, Francisco J. Rincón, Nadia Khaled, Paolo Roberto Grassi, Vincenzo Rana, David Atienza, Donatella Sciuto:
Model-based design for wireless body sensor network nodes. 1-6 - Ignacio Arnaldo, Alessandro Vincenzi, José Luis Ayala, José Luis Risco-Martín, José Ignacio Hidalgo, Martino Ruggiero, David Atienza:
Fast and scalable temperature-driven floorplan design in 3D MPSoCs. 1-6 - Lars Schor, Iuliana Bacivarov, Hoeseok Yang, Lothar Thiele:
Fast worst-case peak temperature evaluation for real-time applications on multi-core systems. 1-6 - Fayrouz Haddad, Wenceslas Rahajandraibe, Hassen Aziza, Karine Castellani-Coulié, Jean-Michel Portal:
Built-in tuning of RFIC Passive Polyphase Filter by process and thermal monitoring. 1-5 - Manuel J. Barragan Asian, Gildas Léger, José Luis Huertas:
Multi-condition alternate test of analog, mixed-signal, and RF systems. 1-6 - András Timár, Márta Rencz:
Acquiring real-time heating of cells in standard cell designs. 1-5 - Gergely Nagy, András Poppe:
Simulation framework for multilevel power estimation and timing analysis of digital systems allowing the consideration of thermal effects. 1-5 - Maksim Jenihhin, Samary Baranov, Jaan Raik, Valentin Tihhomirov:
PSL assertion checkers synthesis with ASM based HLS tool ABELITE. 1-6 - Ozgur Sinanoglu, Vishwani D. Agrawal:
Retiming scan circuit to eliminate timing penalty. 1-6 - Karine Castellani-Coulié, Hassen Aziza, Wenceslas Rahajandraibe, Gilles Micolau, Jean-Michel Portal:
Investigation of a CMOS oscillator concept for particle detection and diagnosis. 1-5 - Gilles Micolau, Karine Castellani-Coulié, Hassen Aziza, Jean-Michel Portal:
SITARe: A simulation tool for analysis and diagnosis of radiation effects. 1-5 - Guilherme Schwanke Cardoso, Tiago R. Balen, Marcelo Soares Lubaszewski, Rafael Galhardo Vaz, Odair Lelis Goncalez:
Impact of TID-induced threshold deviations in analog building-blocks of operational amplifiers. 1-6 - Raul Chipana, Fernanda Lima Kastensmidt, Jorge L. Tonfat, Ricardo Reis:
SET susceptibility estimation of clock tree networks from layout extraction. 1-6 - Jose Eduardo Pereira Souza, Fernanda Lima Kastensmidt:
Applying adaptive temporal filtering for SET mitigation based on the propagation-delay of every logical path. 1-6 - Wassim Mansour, Raoul Velazco:
SEU fault-injection in VHDL-based processors: A case study. 1-5 - Eduardo Chielle, Raul Sergio Barth, Angelo Cardoso Lapolli, Fernanda Lima Kastensmidt:
Configurable tool to protect processors against SEE by software-based detection techniques. 1-6 - Jefferson Paulo Koppe, Elias P. Duarte Jr., Luis C. E. Bona:
MoDiVHA: A hierarchical strategy for distributed test assignment. 1-6 - A. Wecxsteen, Salma Bergaoui, Régis Leveugle:
Detailed analysis of compilation options for robust software-based embedded systems. 1-6 - Samuel Nascimento Pagliarini, Lirida A. B. Naviner, Jean-François Naviner:
Selective hardening methodology for combinational logic. 1-6 - Mohamed Ben Jrad, Régis Leveugle:
Pattern-based injections in processors implemented on SRAM-based FPGAs. 1-4 - Frederico Ferlini, Felipe A. da Silva, Eduardo Augusto Bezerra, Djones Vinicius Lettnin:
Non-intrusive fault tolerance in soft processors through circuit duplication. 1-6
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