default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDISSS 2001: Montréal, Québec, Canada
- Román Hermida, El Mostapha Aboulhamid:
Proceedings of the 14th International Symposium on Systems Synthesis, ISSS 2001, Montrél, Québec, Canada, September 30 - October 3, 2001. ACM / IEEE Computer Society 2001, ISBN 1-58113-418-5
Memory optimization methodologies
- Om Prakash Gangwal, André Nieuwland, Paul E. R. Lippens:
A scalable and flexible data synchronization scheme for embedded HW-SW shared-memory systems. 1-6 - Mahmut T. Kandemir, Ismail Kadayif, Ugur Sezer:
Exploiting scratch-pad memory using Presburger formulas. 7-12 - Tycho van Meeuwen, Arnout Vandecappelle, Allert van Zelst, Francky Catthoor, Diederik Verkest:
System-level interconnect architecture exploration for custom memory organizations. 13-18 - Samy Meftali, Ferid Gharsalli, Frédéric Rousseau, Ahmed Amine Jerraya:
An optimal memory allocation for application-specific multiprocessor system-on-chip. 19-24 - Peter Grun, Nikil D. Dutt
, Alexandru Nicolau:
APEX: Access Pattern Based Memory Architecture Exploration. 25-32
Keynote
- Luca Benini, Giovanni De Micheli:
Powering Networks on Chips: Energy-Efficient and Reliable Interconnect Design for SoCs. 33-38
H/S Embedded Systems
- Kaiyu Chen, Sharad Malik, David I. August:
Retargetable static timing analysis for embedded software. 39-44 - Per Bjuréus, Axel Jantsch:
Performance analysis with confidence intervals for embedded software processes. 45-50 - Cristiana Bolchini, Luigi Pomante, Fabio Salice, Donatella Sciuto:
On-line fault detection in a hardware/software co-design environment. 51-56 - Gunnar Braun, Andreas Hoffmann, Achim Nohl, Heinrich Meyr:
Using static scheduling techniques for the retargeting of high speed, compiled simulators for embedded processors from an abstract machine description. 57-62 - Haris Lekatsas, Jörg Henkel, Wayne H. Wolf:
Design and simulation of a pipelined decompression architecture for embedded systems. 63-68
Special Session on Design Paradigms
- Brian Bailey, Daniel Gajski:
RTL semantics and methodology. 69-74 - Preeti Ranjan Panda:
SystemC: A Modeling Platform Supporting Multiple Design Abstractions. 75-80 - Masahiro Fujita, Hiroshi Nakamura:
The standard SpecC language. 81-86 - Frederic Doucet, Rajesh K. Gupta, Masato Otsuka, Patrick Schaumont, Sandeep K. Shukla:
Interoperability as a design issue in C++ based modeling environments. 87-92 - Guang R. Gao:
Bridging the gap between ISA compilers and silicon compilers a challenge for future SoC design. 93
Panel
- Wolfgang Rosenstiel, Brian Bailey, Masahiro Fujita, Guang R. Gao, Rajesh K. Gupta, Preeti Ranjan Panda:
New Design Paradigms: What Needs to be Standardized?. 94
Memory aspects in system design
- Antoine Fraboulet, Karen Kodary, Anne Mignotte:
Loop fusion for memory space optimization. 95-100 - Preeti Ranjan Panda, Luc Séméria, Giovanni De Micheli:
Cache-efficient memory layout of aggregate data structures. 101-106 - Miguel Miranda, C. Ghez, Chidamber Kulkarni, Francky Catthoor, Diederik Verkest:
Systematic speed-power memory data-layout exploration for cache controlled embedded multimedia applications. 107-112 - Peter Petrov, Alex Orailoglu:
Data cache energy minimizations through programmable tag size matching to the applications. 113-117 - Marco Bekooij, Jochen A. G. Jess, Jef L. van Meerbergen:
Phase coupled operation assignment for VLIW processors with distributed register files. 118-123
Synthesis for Low Power
- Lama H. Chandrasena, Priyadarshana Chandrasena, Michael J. Liebelt:
An energy efficient rate selection algorithm for voltage quantized dynamic voltage scaling. 124-129 - Radu Muresan, Catherine H. Gebotys:
Current consumption dynamics at instruction and program level for a VLIW DSP processor. 130-135 - Giovanni Beltrame, Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto, Vito Trianni:
Dynamic modeling of inter-instruction effects for execution time estimation. 136-141 - Ansgar Stammermann, Lars Kruse, Wolfgang Nebel, Alexander Pratsch, Eike Schmidt, Milan Schulte, Arne Schulz:
System level optimization and design space exploration for low power. 142-146 - Kyu-won Choi, Abhijit Chatterjee:
Efficient instruction-level optimization methodology for low-power embedded systems. 147-152 - Eui-Young Chung, Luca Benini, Giovanni De Micheli:
Source code transformation based on software cost analysis. 153-158
High Level and Architectural Synthesis
- Qin Zhao, Twan Basten, Bart Mesman, C. A. J. van Eijk, Jochen A. G. Jess:
Static resource models of instruction sets. 159-164 - Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay:
Combined instruction and loop parallelism in array synthesis for FPGAs. 165-170 - Sumit Gupta, Nick Savoiu, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau:
Conditional speculation and its effects on performance and area for high-level snthesis. 171-176 - Marcos Sánchez-Élez, Milagros Fernández, Román Hermida, Rafael Maestre, Fadi J. Kurdahi, Nader Bagherzadeh:
A data scheduler for multi-context reconfigurable architectures. 177-182 - Zhong Wang, Qingfeng Zhuge, Edwin Hsing-Mean Sha:
Scheduling and partitioning for multiple loop nests. 183-188 - Tommy Kuhn, Tobias Oppold, C. Schulz-Key, Markus Winterholer, Wolfgang Rosenstiel, Mark Edwards, Yaron Kashai:
Object oriented hardware synthesis and verification. 189-194
Special Session on Network Processors: An Industrial Perspective
- Pierre G. Paulin:
Embedded systems technologies for application-specific architecture platforms. 195 - Richard Norman:
System design of a telecommunication router. 196 - Feliks J. Welfeld:
Network processing in content inspection applications. 197-201
Panel
- Ahmed Amine Jerraya, Pierre G. Paulin, Richard Norman, Feliks J. Welfeld:
Programming models for network processors (Panel). 202
IP Design and Reuse
- Chien-In Henry Chen:
Synthesis of configurable linear feedback shifter registers for detecting random-pattern-resistant faults. 203-208 - Noureddine Chabini, Yvon Savaria:
Methods for optimizing register placement in synchronous circuits derived using software pipelining techniques. 209-214 - Maria-Cristina V. Marinescu, Martin C. Rinard:
High-level automatic pipelining for sequential circuits. 215-220 - Joonseok Park, Pedro C. Diniz:
Synthesis of pipelined memory access controllers for streamed data applications on FPGA-based computing engines. 221-226 - Alessandro Fin, Franco Fummi, Giovanni Perbellini:
Soft-cores generation by instruction set analysis. 227-232 - Hung-Pin Wen, Chien-Yu Lin, Youn-Long Lin:
Concurrent-simulation-based remote IP evaluation over the internet for system-on-a-chip design. 233-238 - Pontus Åström, Stefan Johansson, Peter Nilsson:
Application of Software design patterns to DSP library design. 239-243
Formal Aspects and Distributed Systems
- Ying Zhao, Sharad Malik, Matthew W. Moskewicz, Conor F. Madigan:
Accelerating boolean satisfiability through application specific processing. 244-249 - Marcus T. Schmitz, Bashir M. Al-Hashimi:
Considering power variations of DVS processing elements for energy minimisation in distributed systems. 250-255 - Prabhat Mishra, Nikil D. Dutt, Alexandru Nicolau:
Functional abstraction driven design space exploration of heterogeneous programmable architectures. 256-261 - JoAnn M. Paul, Arne J. Suppé, Donald E. Thomas:
Modeling and simulation of steady state and transient behaviors for emergent SoCs. 262-267 - Ahmed Khoumsi:
Synthesizing distributed real-time systems modeled by a timed version of a subset of LOTOS. 268-273 - Abhijit K. Deb, Johnny Öberg, Axel Jantsch:
Control and communication performance analysis of embedded DSP systems in the MASIC methodology. 274-273
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2026-06-16 22:39 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
