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ORCIDSoC 2006: Tampere, Finland
- International Symposium on System-on-Chip, SoC 2006, Tampere, Finland, November 13-16, 2006. IEEE 2006, ISBN 1-4244-0621-8
- Steve Leibson:
The Future of Nanometer SOC Design. 1-6 - Kamil Synek:
Using SPIRIT Cores in SonicsStudio. 1-4 - Paul M. Heysters:
IP Reuse for Flexible & Efficient DSP Platform Chips. 1 - Vesa Lahtinen:
System Level Design Experiences and the Need for Standardization. 1-4 - Sungdae Choi, Kyomin Sohn, Hyejung Kim, Joo-Young Kim, Seong-Jun Song, Namjun Cho, Jerald Yoo
, Hoi-Jun Yoo:
An Ultra Low-Power Body Sensor Network Control Processor with Centralized Node Control. 1-4 - Kim Rounioja, Kimmo Puusaari:
Implementation of an HSDPA Receiver with a Customized Vector Processor. 1-4 - Daniel Mesquita, Benoît Badrignans, Lionel Torres, Gilles Sassatelli, Michel Robert, Fernando Gehm Moraes:
A Leak Resistant SoC to Counteract Side Channel Attacks. 1-4 - Daniel Iancu, Hua Ye, Vladimir Kotlyar, Murugappan Senthilvelan, John Glossner, Gary Nacer, Andrei Iancu, Jarmo Takala:
Analog Television, WiMAX and DVB-H on the Same SoC Platform. 1-4 - Thomas Eckart, Martin Schnieringer:
Development and Verification of Embedded Firmware using Virtual System Prototypes. 1 - Fabrizio Ferrandi, Marco Novati, Massimo Morandi, Marco D. Santambrogio, Donatella Sciuto:
Dynamic Reconfiguration: Core Relocation via Partial Bitstreams Filtering with Minimal Overhead. 1-4 - Blagomir Donchev, Georgi Kuzmanov, Georgi Nedeltchev Gaydadjiev:
External Memory Controller for Virtex II Pro. 1-4 - Stamatis Vassiliadis, Ioannis Sourdis:
Reconfigurable Fabric Interconnects. 1-4 - Perttu Salmela, Risto Mäkinen, Pekka Jääskeläinen, Jarmo Takala:
Loop Scheduling for Transport Triggered Architecture Processors. 1-4 - Masoud Daneshtalab, Ali Afzali-Kusha, Siamak Mohammadi:
Minimizing Hot Spots in NoCs through a Dynamic Routing Algorithm based on Input and Output Selections. 1-4 - J. Balachandran, Maarten Kuijk, Steven Brebels, Geert Carchon, Walter De Raedt, Bart Nauwelaers, Eric Beyne:
Efficient Link Architecture for On-Chip Serial links and Networks. 1-4 - Rabie Ben Atitallah, Lossan Bonde, Smaïl Niar, Samy Meftali, Jean-Luc Dekeyser:
Multilevel MPSoC Performance Evaluation Using MDE Approach. 1-4 - Gert Goossens, Dirk Lanneer, Werner Geurts, Johan Van Praet:
Design of ASIPs in multi-processor SoCs using the Chess/Checkers retargetable tool suite. 1-4 - Wojciech Sakowski, Wlodzimierz Wrona, Sebastian Kaprowski, Maciej Przybysz:
Enhanced legacy 68000 instruction set architecture as a basis for system on chip development. 1-4 - Leandro Soares Indrusiak:
Exploring Application-Level Concurrency in SoC Design. 1-4 - Heikki Orsila, Tero Kangas, Erno Salminen, Timo Hämäläinen:
Parameterizing Simulated Annealing for Distributing Task Graphs on Multiprocessor SoCs. 1-4 - Martti Forsell:
Realizing Multioperations for Step Cached MP-SOCs. 1-6 - Yang Qu, Juha-Pekka Soininen, Jari Nurmi:
Using Constraint Programming to Achieve Optimal Prefetch Scheduling for Dependent Tasks on Run-Time Reconfigurable Devices. 1-4 - Claudio Brunelli, Jari Nurmi:
Design And Verification of a VHDL Model of a Floating-Point Unit for a RISC Microprocessor. 1-4 - Markus Winter, Gerhard P. Fettweis:
Interconnection Generation for System-on-Chip Design. 1-4 - Yaseer Arafat Durrani, Teresa Riesgo:
Power Estimation for IP-Based Modules. 1-4 - Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi:
Serial Bus Encoding for Low Power Application. 1-4 - Gabriel Caffarena, Juan A. López, Carlos Carreras, Octavio Nieto-Taladriz:
Optimized Synthesis of DSP Cores Combining Logic-based and Embedded FPGA Resources. 1-4 - Pekka Rantala, Teijo Lehtonen, Jouni Isoaho, Juha Plosila:
Fault-tolerant Routing Approach for Reconfigurable Networks-on-Chip. 1-4 - Konrad Engel, Thomas Kalinowski, Roger Labahn, Frank Sill, Dirk Timmermann:
Algorithms for Leakage Reduction with Dual Threshold Design Techniques. 1-4 - Aline Mello, Leonel Tedesco, Ney Calazans, Fernando Moraes:
Evaluation of current QoS Mechanisms in Networks on Chip. 1-4 - Robert Mullins:
Minimising Dynamic Power Consumption in On-Chip Networks. 1-4 - Srinivasan Murali, Rutuparna Tamhankar, Federico Angiolini, Antonio Pullini, David Atienza, Luca Benini, Giovanni De Micheli:
Comparison of a Timing-Error Tolerant Scheme with a Traditional Re-transmission Mechanism for Networks on Chips. 1-4 - Abdelhafid Bouhraoua, Muhammad E. S. Elrabaa:
A High-Throughput Network-on-Chip Architecture for Systems-on-Chip Interconnect. 1-4 - Sankalita Saha, Sebastian Puthenpurayil, Shuvra S. Bhattacharyya:
Dataflow Transformations in High-level DSP System Design. 1-6 - Perttu Salmela, Chung-Ching Shen, Shuvra S. Bhattacharyya, Jarmo Takala:
Register File Partitioning with Constraint Programming. 1-4 - Tomi Westerlund, Juha Plosila:
Formal Modelling of Multiclocked SoC Systems. 1-4 - Mahtab Niknahad, Kamran Saleh, Mehrdad Najibi, Hossein Pedram:
High-Level Optimization of Asynchronous Systems Utilizing Conditional Restructuring. 1-6 - Martin Holzer, Bastian Knerr, Markus Rupp:
Structural Verification in Minimal Time. 1-4 - Nehir Sönmez, Arda Yurdakul:
SIxD: A Configurable Application-Specific SISD/SIMD Microprocessor Soft-Core. 1-4 - David Castells-Rufas, Jaume Joven, Jordi Carrabina:
A Validation And Performance Evaluation Tool for ProtoNoC. 1-4 - Ethiopia Nigussie, Sampo Tuuna, Juha Plosila, Jouni Isoaho:
Analysis of Crosstalk and Process Variations Effects on On-Chip Interconnects. 1-4 - Pascal T. Wolkotte, Marcel D. van de Burgwal, Gerard J. M. Smit:
Non-Power-of-Two FFTs: Exploring the Flexibility of the MONTIUM. 1-4 - Jari Heikkinen, Jarmo Takala:
Programmability in Dictionary-Based Compression. 1-4 - Stefan Valentin Gheorghita, Twan Basten, Henk Corporaal:
Application Scenarios in Streaming-Oriented Embedded System Design. 1-4 - Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich:
Hardware Cost Analysis for Weakly Programmable Processor Arrays. 1-4 - Martino Ruggiero, Pari Gioia, Guerri Alessio, Luca Benini, Michela Milano, Davide Bertozzi, Alexandru Andrei:
A Cooperative, Accurate Solving Framework for Optimal Allocation, Scheduling and Frequency Selection on Energy-Efficient MPSoCs. 1-4 - Sohini Dasgupta, Alex Yakovlev:
Modeling And Performance Analysis of GALS architectures. 1-4 - Erno Salminen, Tero Kangas, Timo Hämäläinen:
The Impact of Communication on the Scalability of the Data-parallel Video Encoder on MPSoC. 1-4 - Chantal Ykman-Couvreur, Vincent Nollet, Francky Catthoor, Henk Corporaal:
Fast Multi-Dimension Multi-Choice Knapsack Heuristic for MP-SoC Run-Time Management. 1-4
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