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ORCID20th ISQED 2019: Santa Clara, California, USA
- 20th International Symposium on Quality Electronic Design, ISQED 2019, Santa Clara, CA, USA, March 6-7, 2019. IEEE 2019, ISBN 978-1-7281-0392-1
SESSION 1A: Machine Learning in Conventional and Emerging Platforms
- Ming Yan, Yuntao Song, Yiyu Feng, Ghasem Pasandi, Massoud Pedram, Shahin Nazarian:
kNN-CAM: A k-Nearest Neighbors-based Configurable Approximate Floating Point Multiplier. 1-7 - Arman Roohi, Shaahin Angizi, Deliang Fan, Ronald F. DeMara
:
Processing-In-Memory Acceleration of Convolutional Neural Networks for Energy-Effciency, and Power-Intermittency Resilience. 8-13 - Amir Erfan Eshratifar, Amirhossein Esmaili, Massoud Pedram:
Towards Collaborative Intelligence Friendly Architectures for Deep Learning. 14-19 - Haowen Fang, Amar Shrestha, Ziyi Zhao, Yanzhi Wang, Qinru Qiu:
A General Framework to Map Neural Networks onto Neuromorphic Processor. 20-25
SESSION 1B: Modern High-Level and Logic Synthesis
- Ghasem Pasandi, Shahin Nazarian, Massoud Pedram:
Approximate Logic Synthesis: A Reinforcement Learning-Based Technology Mapping Approach. 26-32 - Chaofan Li, Sachin S. Sapatnekar, Jiang Hu:
Fast Mapping-Based High-Level Synthesis of Pipelined Circuits. 33-38 - Barkha Gupta, W. Rhett Davis:
Characterization of Fast, Accurate Leakage Power Models for IEEE P2416. 39-44 - Yukio Miyasaka, Ashish Mittal, Masahiro Fujita:
Synthesis of Algorithm Considering Communication Structure of Distributed/Parallel Computing. 45-51
SESSION 1C: Emerging Memory and Spintronics Technologies for Future Energy Efficient Applications
- Masoud Zabihi, Zhengyang Zhao, D. C. Mahendra, Zamshed I. Chowdhury, Salonik Resch, Thomas Peterson, Ulya R. Karpuzcu, Jianping Wang, Sachin S. Sapatnekar:
Using Spin-Hall MTJs to Build an Energy-Efficient In-memory Computation Platform. 52-57 - Sonal Shreya, Brajesh Kumar Kaushik:
Low Restoration-Energy Differential Spin Hall Effect MRAM for High-Speed Nonvolatile SRAM Application. 58-63 - Sherif Amer, Garrett S. Rose:
A Multi-Driver Write Scheme for Reliable and Energy Efficient 1S1R ReRAM Crossbar Arrays. 64-69 - Vaibhav Agarwal, Sneh Saurabh:
Application of Probabilistic Spin Logic (PSL) in Detecting Satisfiability of a Boolean Function. 70-75
SESSION 2A: Advances in Simulation, Design Optimization and Debug
- Xu Liu, Alessandro Bernardini, Ulf Schlichtmann, Xing Zhou:
A Compact Model of Negative Bias Temperature Instability Suitable for Gate-Level Circuit Simulation. 76-80 - Pradeep Chawda, Anupriya Prasad, Kunjal Rathod, Kritika Solanki:
An Automated Design Flow for Synthesis of Optimal Switching Power Supply. 81-84 - Prateek Gupta, Harshini Mandadapu, Shirisha Gourishetty, Zia Abbas:
Robust Transistor Sizing for Improved Performances in Digital Circuits using Optimization Algorithms. 85-91 - Zheng Xu, Jacob Abraham:
Resilient Reorder Buffer Design for Network-on-Chip. 92-97 - Zhipeng Dong, Xi Cao, M. Ahosan Ul Karim, Vivek Joshi, Torsten Klick, Joerg Schmid:
Simulation Based Assessment of SRAM Data Retention Voltage. 98-103
SESSION 2B: System Level Tools, Flows, Methods
- Mohamad Hammam Alsafrjalani, Tosiron Adegbija, Lokesh Ramamoorthi:
Evaluating Design Space Subsetting for Multi-Objective Optimization in Configurable Systems. 104-109 - Xiaokun Yang, Yunxiang Zhang, Lei Wu:
A Scalable Image/Video Processing Platform with Open Source Design and Verification Environment. 110-116 - Jitumani Sarma, Akash Katiyar, Rakesh Biswas, Hemanta Kumar Mondal:
Power-aware IoT based Smart Health Monitoring using Wireless Body Area Network. 117-122 - Jawad Haj-Yahya, Efraim Rotem, Avi Mendelson, Anupam Chattopadhyay:
A Comprehensive Evaluation of Power Delivery Schemes for Modern Microprocessors. 123-130 - Kaustav Goswami, Hemanta Kumar Mondal, Shirshendu Das, Dip Sankar Banerjee:
State Preserving Dynamic DRAM Bank Re-Configurations for Enhanced Power Efficiency. 131-137
SESSION 2C: High Performance Application Specific Architecture
- Alexander J. Groszewski, Travis Lenz:
Deterministic Stochastic Computation Using Parallel Datapaths. 138-144 - Joonseop Sim, Minsu Kim, Yeseong Kim, Saransh Gupta, Behnam Khaleghi, Tajana Rosing:
MAPIM: Mat Parallelism for High Performance Processing in Non-volatile Memory Architecture. 145-150 - Kazuaki Hara, Naoki Takeuchi, Masashi Aono, Yuko Hara-Azumi:
Amoeba-Inspired Stochastic Hardware SAT Solver. 151-156 - M. Hassan Najafi, S. Rasoul Faraji, Bingzhe Li, David J. Lilja, Kia Bazargan:
Accelerating Deterministic Bit-Stream Computing with Resolution Splitting. 157-162 - Prabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar:
High-Performance NoCs Employing the DSP48E1 Blocks of the Xilinx FPGAs. 163-169
SESSION 3A: Deep Learning Circuits and Architectures
- Dharanidhar Dhang, Syed Ali Hasnain, Rabi N. Mahapatra:
MReC: A Multilayer Photonic Reservoir Computing Architecture. 170-175 - Maedeh Hemmat, Azadeh Davoodi:
Dynamic Reconfiguration of CNNs for Input-Dependent Approximation. 176-182 - Sumon Dey, Paul D. Franzon:
An Application Specific Processor Architecture with 3D Integration for Recurrent Neural Networks. 183-190 - Anurag Reddy Daram, Dhireesha Kudithipudi, Angel Yanguas-Gil:
Task-Based Neuromodulation Architecture for Lifelong Learning. 191-197
SESSION 3B: Innovations In Classic Hardware Security Problems
- Qian Wang, Mingze Gao, Gang Qu:
PUF-PassSE: A PUF based Password Strength Enhancer for IoT Applications. 198-203 - Yasaswy Kasarabada, Suyuan Chen, Ranga Vemuri:
On SAT-Based Attacks On Encrypted Sequential Logic Circuits. 204-211 - Matthew Lewandowski, Srinivas Katkoori:
A Darwinian Genetic Algorithm for State Encoding Based Finite State Machine Watermarking. 210-215 - Jawad Haj-Yahya, Ming Ming Wong, Vikramkumar Pudi, Shivam Bhasin, Anupam Chattopadhyay:
Lightweight Secure-Boot Architecture for RISC-V System-on-Chip. 216-223
SESSION 3C: Co-Optimization of Device Performance and Design Reliability from State-of-the-art FinFET to Quantum Technologies
- Alvin D. Wong, Kevin Su, Hang Sun, Arash Fayyazi, Massoud Pedram, Shahin Nazarian:
VeriSFQ: A Semi-formal Verification Framework and Benchmark for Single Flux Quantum Technology. 224-230 - Ya-Chi Huang, Meng-Hsueh Chiang, Shui-Jinn Wang:
Speed Optimization of Vertically Stacked Gate-All-Around MOSFETs with Inner Spacers for Low Power and Ultra-Low Power Applications. 231-234 - Vidya A. Chhabria, Sachin S. Sapatnekar:
Impact of Self-heating on Performance and Reliability in FinFET and GAAFET Designs. 235-240 - Hung-Han Lin, Vita Pi-Ho Hu:
Device Designs and Analog Performance Analysis for Negative-Capacitance Vertical-Tunnel FET. 241-246
SESSION 4A: Artificial Intelligence for Efficient Application Specific Hardware
- Huan Yu, Jaemin Shin, Tim Michalka, Mourad Larbi, Madhavan Swaminathan:
Behavioral Modeling of Tunable I/O Drivers with Pre-emphasis Using Neural Networks. 247-252 - Kenshu Seto, Hamid Nejatollahi, Jiyoung An, Sujin Kang, Nikil D. Dutt:
Small Memory Footprint Neural Network Accelerators. 253-258 - Morteza Hosseini, Hirenkumar Paneliya, Utteja Kallakuri, Mohit Khatwani, Tinoosh Mohsenin:
Minimizing Classification Energy of Binarized Neural Network Inference for Wearable Devices. 259-264 - Katayoun Neshatpour, Farnaz Behnia, Houman Homayoun, Avesta Sasan:
Exploiting Energy-Accuracy Trade-off through Contextual Awareness in Multi-Stage Convolutional Neural Networks. 265-270
SESSION 4B: Verification, ATPG and Failure Analysis
- Xiaobang Liu, Ranga Vemuri:
Assertion Coverage Aware Trace Signal Selection in Post-Silicon Validation. 271-277 - Yuting Cao, Hao Zheng, Sandip Ray:
A Communication-Centric Observability Selection for Post-Silicon System-on-Chip Integration Debug. 278-283 - Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita:
Automatic Test Pattern Generation for Double Stuck-at Faults Based on Test Patterns of Single Faults. 284-290 - Tsutomu Ishida, Izumi Nitta, Daisuke Fukuda, Yuzi Kanazawa:
Deep Learning-Based Wafer-Map Failure Pattern Recognition Framework. 291-297
SESSION 5A: Physical Design Optimization
- A. K. M. Mahfuzul Islam, Shinichi Nishizawa, Yusuke Matsui, Yoshinobu Ichida:
Drive-Strength Selection for Synthesis of Leakage-Dominant Circuits. 298-303 - Billy Huggins, W. Rhett Davis, Paul D. Franzon:
Estimating Pareto Optimum Fronts to Determine Knob Settings in Electronic Design Automation Tools. 304-310 - Madhu Raman, Nizar Abdallah, Julien Dunoyer:
An Artificial Intelligence Approach to EDA Software Testing: Application to Net Delay Algorithms in FPGAs. 311-316 - Rung-Bin Lin, Yu-Xiang Chiang:
Impact of Double-Row Height Standard Cells on Placement and Routing. 317-322
SESSION 5B.1: 3D Integration & Advanced Packaging
- Shantonu Das, Dae Hyun Kim:
A Non-Slicing 3-D Floorplan Representation for Monolithic 3-D IC Design. 323-328 - Sheng-En David Lin, Dae Hyun Kim:
Routing Complexity Minimization of Monolithic Three-Dimensional Integrated Circuits. 329-334
SESSION 5B.2: Future of SOC Architectures and Verification
- Antara Ganguly, Rajeev Muralidhar, Virendra Singh:
Towards Energy Efficient non-von Neumann Architectures for Deep Learning. 335-342 - Pranav Ashar, Vinod Viswanath:
Closing the Verification Gap with Static Sign-off. 343-347
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