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ORCID37th ISMVL 2007: Oslo, Norway
- 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, 13-16 May 2007, Oslo, Norway. IEEE Computer Society 2007, ISBN 978-0-7695-2831-1
Keynote
- Valeriu Beiu
:
Grand Challenges of Nanoelectronics and Possible Architectural Solutions: What Do Shannon, von Neumann, Kolmogorov, and Feynman Have to do with Moore.
Invited Paper
- Mark Glusker:
The Ternary Calculating Machine of Thomas Fowler.
Theory 1
- Viorica Sofronie-Stokkermans, Carsten Ihlemann:
Automated Reasoning in Some Local Extensions of Ordered Structures. 1 - Radomir S. Stankovic, Jaakko Astola:
Reading the Sampling Theorem in Multiple-Valued Logic: A Journey from the (Shannong) Sampling Theorem to the Shannon Decomposition Rule. 2 - Heng Zhang, Mingyi Zhang:
Model-Characterizing Formulas and Normal Forms in Godel Logics. 3
Logic Functions
- Claudio Moraga, Milena Stankovic, Suzana Stojkovic:
Spectral Analysis of Special Properties of Ternary Functions. 4 - Shinobu Nagayama, Tsutomu Sasao:
Representations of Elementary Functions Using Edge-Valued MDDs. 5 - Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel:
Experimental Studies on SAT-Based ATPG for Gate Delay Faults. 6
Theory 2 (Clones)
- Hajime Machida, Michael Pinsker:
Polynomials as Generators of Minimal Clones. 7 - Boris A. Romov:
Restriction-Closed Hyperclones. 8 - Lucien Haddad, Hajime Machida, Ivo G. Rosenberg:
Monoidal Intervals of Partial Clones. 9
Quantum Computing 1
- D. Michael Miller, David Y. Feinstein, Mitchell A. Thornton:
Variable Reordering and Sifting for QMDD. 10 - Mozammel H. A. Khan, Marek A. Perkowski:
GF(4) Based Synthesis of Quaternary Reversible/Quantum Logic Circuits. 11 - Yale Fan:
A Generalization of the Deutsch-Jozsa Algorithm to Multi-Valued Quantum Logic. 12
Theory 3
- Igor N. Aizenberg, Claudio Moraga:
The Genetic Code as a Multiple-Valued Function and Its Implementation Using Multilayer Neural Network Based on Multi-Valued Neurons. 13 - Arnon Avron, Anna Zamansky:
Non-deterministic Multi-valued Matrices for First-Order Logics of Formal Inconsistency. 14 - Bogdan J. Falkowski, Cicilia C. Lozano, Tadeusz Luba:
New Fastest Linearly Independent Transforms over GF(3). 15 - Nabil Abu-Khader, Pepe Siy:
Inversion/Division in Galois Field Using Multiple-Valued Logic. 16
Quantum Computing 2
- Rusins Freivalds, Liva Garkaje:
Boolean Functions of Low Polynomial Degree for Quantum Query Complexity Theory. 17 - Arushi Raghuvanshi, Yale Fan, Michal Woyke, Marek A. Perkowski:
Quantum Robots for Teenagers. 18 - Martin Lukac, Marek A. Perkowski:
Quantum Mechanical Model of Emotional Robot Behaviors. 19 - Asif Islam Khan, Nadia Nusrat, Samira Manabi Khan, Masud Hasan, Mozammel H. A. Khan:
Quantum Realization of Some Ternary Circuits Using Muthukrishnan-Stroud Gates. 20
Theory 4
- Witold Charatonik, Michal Wrona:
2-SAT Problems in Some Multi-Valued Logics Based on Finite Lattices. 21 - Carlos Ansótegui, Maria Luisa Bonet, Jordi Levy, Felip Manyà:
A Complete Resolution Calculus for Signed Max-SAT. 22 - Bogdan J. Falkowski, Cicilia C. Lozano, Tadeusz Luba:
Efficient Algorithm for Calculation of Quaternardy Fixed Polarity Arithmetic Expansions. 23
Circuit Design 1
- Krzysztof S. Berezowski, Sarma B. K. Vrudhula:
Multiple-Valued Logic Circuits Design Using Negative Differential Resistance Devices. 24 - Nobuaki Okada, Michitaka Kameyama:
Low-Power Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits. 25 - Yasushi Yuminaka, Kazuyoshi Yamamura:
Equalization Techniques for Multiple-Valued Data Transmission and Their Application. 26
Theory 5
- Patrik Eklund, Maria A. Galán:
The Rough Powerset Monad. 27 - Dragan Jankovic, Radomir S. Stankovic, Claudio Moraga:
Exploiting Homogeneous Dual Polarity Routes in Implementation of Algorithms for Optimization of Galois Field Expressions for Ternary Functions. 28 - Jun Liu, Luis Martínez-López, Yang Xu, Zhirui Lu:
Automated Reasoning Algorithm for Linguistic Valued Lukasiewicz Propositional Logic. 29
Circuit Design 2
- Henning Gundersen, Yngvar Berg:
Fast Addition Using Balanced Ternary Counters Designed with CMOS Semi-Floating Gate Devices. 30 - Naofumi Homma, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi:
Algorithm-Level Optimization of Multiple-Valued Arithmetic Circuits Using Counter Tree Diagrams. 31 - Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura:
On Designs of Radix Converters Using Arithmetic Decompositions--Binary to Decimal Converters--. 32
Theory 6
- Dan A. Simovici:
On the Axiomatization of Generalized Entropic Metrics. 33 - Lucien Haddad, Dietlinde Lau:
Characterization of Partial Sheffer Functions in 3-Valued Logic. 34 - Yoshinori Yamamoto:
Power Indexes in Voting Systems and Multiple-Valued Logic. 35
Circuit 3
- Tomoki Tanoue, Munehiko Nagatani, Takao Waho:
A Ternary Analog-to-Digital Converter System. 36 - Renè Jensen, Yngvar Berg:
Dual Data-Rate Cyclic D/A Converter Using Semi Floating-Gate Devices. 37 - Yngvar Berg, Renè Jensen, Johannes Goplen Lomsdalen, Henning Gundersen, Snorre Aunet:
Fault Tolerant CMOS Logic Using Ternary Gates. 38
Theory 7
- Tasuku Ito, Michitaka Kameyama:
Universal VLSI Based on a Redundant Multiple-Valued Sequential Logic Operation. 39 - Tsutomu Sasao:
An Application of 16-Valued Logic to Design of Reconfigurable Logic Arrays. 40 - Milena Stankovic, Suzana Stojkovic, Claudio Moraga:
Linearization of Ternary Decision Diagrams by Using the Polynomial Chrestenson Spectrum. 41
Circuit Design 4
- André Sülflow, Rolf Drechsler:
Modeling a Fully Scalable Reed-Solomon Encoder/Decoder over GF(p^{m}) in SystemC. 42 - Hirokatsu Shirahama, Akira Mochizuki, Takahiro Hanyu, Masami Nakajima, Kazutami Arimoto:
Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor. 43 - Tomohiro Takahashi, Kazuyasu Mizusawa, Takahiro Hanyu:
Asynchronous Peer-to-Peer Simplex/Duplex-Compatible Communication System Using a One-Phase Signaling Scheme. 44
Theory 8
- Dietlinde Lau, Masahiro Miyakawa:
Classifications and Enumeration of Bases in P_{3}(2). 45 - Janusz A. Brzozowski, Yuli Ye:
Simulation of Gate Circuits with Feedback in Multi-Valued Algebras. 46 - Bogdan J. Falkowski, Shixing Yan:
Properties and Fast Algorithms for Ternary Walsh Transform. 47 - Mostafa I. H. Abd-El-Barr, Bambang A. B. Sarif:
Weighted and Ordered Direct Cover Algorithms for Minimization of MVL Functions. 48
Circuit Design 5
- Tetsuya Uemura, Takao Marukame, Ken-ichi Matsuda, Masafumi Yamamoto:
Four-State Magnetic Random Access Memory and Ternary Content Addressable Memory Using CoFe-Based Magnetic Tunnel Junctions. 49 - Mahsan Amoui, Daniel Große, Mitchell A. Thornton, Rolf Drechsler:
Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL. 50 - Juan Núñez, José M. Quintana, Maria J. Avedillo:
Limits to a Correct Evaluation in RTD-Based Quaternary Inverters. 51 - Vasilios Lirigis, Elena Dubrova:
Evaluation and Comparison of Threshold Logic Gates. 52
Circuit Design 5
- Donglin Li, Otmane Aït Mohamed, Sa'ed Abed:
Towards First-Order Symbolic Trajectory Evaluation. 53 - Saeed Sharifi Tehrani, Shie Mannor, Warren J. Gross:
Survey of Stochastic Computation on Factor Graphs. 54 - Radomir S. Stankovic, Jaakko Astola:
A Note on Possible Applications of Fourier Representations in Circuit Design over Reprogrammable Technological Platforms. 55
Circuit Design 7
- Ricardo Cunha, Henri Boudinov, Luigi Carro:
Quaternary Look-Up Tables Using Voltage-Mode CMOS Logic Design. 56 - Akira Mochizuki, Masatomo Miura, Takahiro Hanyu:
High-Performance Multiple-Valued Comparator Based on Active-Load Dual-Rail Differential Logic for Crosstalk-Noise Reduction. 57 - Motoi Inaba:
Experiment Result of Down Literal Circuit and Analog Inverter on CMOS Double-Polysilicon Process. 58
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