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ORCIDHOTI 2025: San Jose, CA, USA
- IEEE Symposium on High-Performance Interconnects, HOTI 2025, San Jose, CA, USA, August 20-22, 2025. IEEE 2025, ISBN 979-8-3315-4888-9
- Timo Schneider, Pengcheng Xu, Torsten Hoefler:
FPsPIN: An FPGA-Based Open-Hardware Research Platform for Processing in the Network. 1-11 - Martijn Bastiaan, Christiaan Baaij, Martin Izzard, Felix Klein, Sanjay Lall, Tammo Spalink:
bittide: Control Time, Not Flows. 1-11 - Peter Olcott, Phil Brown, Davor Capalija, Ethan Lockshin, Sid Sheth:
Panel: HotI 2025. 1 - Lang Xu, Kaushik Kandadi Suresh, Quentin Anthony, Nawras Alnaasan, Dhabaleswar K. Panda:
Characterizing Communication Patterns in Distributed Large Language Model Inference. 1-11 - Alejandro Cano
, Cristóbal Camarero, Carmen Martínez, Ramón Beivide:
Deadlock-Free Routing for Full-Mesh Networks Without Using Virtual Channels. 12-24 - Mikhail Bernadskiy, Peter Carson, Thomas Graham, Taylor Groves, Ho John Lee, Eric Yeh:
Accelerating Frontier MoE Training with 3D Integrated Optics. 25-35 - Zhenguo Wu, Keren Bergman:
Silicon Photonic Accelerated Memory Pooling for Efficient Compute Resource Allocation. 36-47 - Zhiyi Hu, Siyuan Shen, Tommaso Bonato, Sylvain Jeaugey, Cedell Alexander, Eric Spada, James Dinan, Jeff R. Hammond, Torsten Hoefler:
Demystifying NCCL: An In-Depth Analysis of GPU Communication Protocols and Algorithms. 48-59 - Bardia Pezeshki, Alex Tselikov, Robert F. Kalman, Suresh Rangarajan, Ivan Huang, Jeff Pepper, Sarah Zou, Howard Rourke, Alasdair Fikouras:
Micro-LED Data Interconnect for Scale-Up Networks with Record Energy Efficiency. 82-86 - Debendra Das Sharma, Swadesh Choudhary, Peter Z. Onufryk, Rob Pelt:
On-Package Memory with Universal Chiplet Interconnect Express (UCIe): A Low Power, High Bandwidth, Low Latency and Low Cost Approach. 87-96
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