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1st AISTECS@HiPEAC 2016: Prague, Czech Republic

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Sören Sonntag, Sandro Bartolini, Giorgos Dimitrakopoulos, José M. García:
Proceedings of the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC 2016, Prague, Czech Republic, January 18, 2016. ACM 2016, ISBN 978-1-4503-4084-7

Network on Chip Architectures

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Muhammad Ridwan Madarbux, Anouk Van Laer, Philip M. Watts, Timothy M. Jones:
Energy Efficient And Low Latency Interconnection Network For Multicast Invalidates In Shared Memory Systems. 1:1-1:6
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Robert Hesse, Natalie D. Enright Jerger:
Hierarchical Clustering for On-Chip Networks. 2:1-2:6
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Gabriele Miorandi, Mahdi Tala, Marco Balboni, Luca Ramini, Davide Bertozzi:
Evolutionary vs. Revolutionary Interconnect Technologies for Future Low-Power Multi-Core Systems. 3:1-3:6

NoC Packet Forwarding Alternatives

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Najwa Salama, Azeddien M. Sllame:
Designing an Efficient MPLS-Based Switch for FAT Tree Network-on-Chip Systems. 4:1-4:6
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Armin Runge, Reiner Kolla:
Consideration of the Flit Size for Deflection Routing based Network-on-Chips. 5:1-5:6

Interconnect Simulation and Modeling

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Nikos Terzenidis, Pavlos Maniotis, Nikos Pleros:
Bringing OptoBoards to HPC-scale environments: An OptoHPC simulation engine. 6:1-6:6
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Sébastien Rumley, Meisam Bahadori, Ke Wen, Dessislava Nikolova, Keren Bergman:
PhoenixSim: Crosslayer Design and Modeling of Silicon Photonic Interconnects. 7:1-7:6
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Rafael K. V. Maeda, Peng Yang, Xiaowen Wu, Zhe Wang, Jiang Xu, Zhehui Wang, Haoran Li, Luan H. K. Duong, Zhifei Wang:
JADE: a Heterogeneous Multiprocessor System Simulation Platform Using Recorded and Statistical Application Models. 8:1-8:6

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