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ORCID34th FCCM 2026: Atlanta, GA, USA
- 34th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2026, Atlanta, GA, USA, May 13-16, 2026. IEEE 2026, ISBN 979-8-3315-5815-4
- Hang Yan, James Yen, Rongbo Zhang, Andrew Boutros, Vaughn Betz:
The Optimal, The Fast, and The Hybrid: Automatic Placement and Routing for AIE Arrays. 1-9 - Milo Liebster, Amin Mohaghegh, Andrew Boutros:
Déjà Vu Packing: Optimizing FPGA Logic Clustering Runtime via Pattern Memoization. 10-18 - Chang Sun, Zhiqiang Que, Bakhtiar Zadeh, Qibin Liu, Kevin H. Alvarez, Wayne Luk, Maria Spiropulu:
HGQ-LUT: Fast LUT-Aware Training and Efficient Architectures for DNN Inference. 19-28 - Jiabin Xu, Wang Fan, Xuegong Zhou, Wei Cao, Jialin Chen, Fengzhe Zhang, Fan Zhang, Xinsheng Yu:
FHPSAC: FPGA-based High-Parallelism SAC Accelerator. 29-37 - Anvitha Ramachandran, Dhruv Parikh, Viktor K. Prasanna:
GraphLeap: Decoupling Graph Construction and Convolution for Vision GNN Acceleration on FPGA. 38-47 - Sae-Byeok Jeong, Tae-Hwan Kim:
Δ2-PSUM: A Low-Latency Soft-Error-Resilient Binary Neural Network Inference Processor. 48-52 - Mohamed Shahawy, Canberk Sönmez, Paolo Ienne:
NetCilk: Extending Task-Level Parallelism Seamlessly across FPGAs. 53-61 - Ahmed Abdelsalam, Vishal Gondaliya, Ezz Hamed, Pragati Medleri Hire Math, Marc Gepigon, Joshua Landgraf, Nadeen Gebara, Bob Groza, Dongwook Lee, Anshuman Verma, Andrew Putnam:
EZCache: Easy Action-Enabled FPGA Caches for Non-Stalling Datapaths in SmartNICs and Beyond. 62-70 - Guoyu Li, Yang Cao, Lucas H. L. Ng, Alexander Charlton, Qianzhou Wang, Will Punter, Philippos Papaphilippou, Ce Guo, Hongxiang Fan, Wayne Luk, Saman P. Amarasinghe, Ajay Brahmakshatriya:
SPAC: Automating FPGA-based Network Switches with Protocol Adaptive Customization. 71-80 - Alexander Philipp Nowosad, Christian Lienen, Marco Platzner:
A Robotics Middleware for FPGAs Supporting Dynamic Function Exchange and Streaming Data Distribution. 81-89 - Shengzhe Lyu, Yuhan She, Patrick S. Y. Hung, Ray C. C. Cheung, Weitao Xu:
ViM-Q: Scalable Algorithm-Hardware Co-Design for Vision Mamba Model Inference on FPGA. 90-99 - Jingyu Wang, Yongjiang Xue, Kailai Zhuang, Mingze Sun, Qingzeng Song:
ReCoVLM: A Reconfigurable FPGA-GPU Co-Design for Edge Vision-Language Inference. 100-108 - Zifan He, Shengyu Ye, Rui Ma, Yang Wang, Jason Cong:
LUT-LLM: Efficient Language Model Inference with Memory-based Computations on FPGAs. 109-118 - Nuntipat Narkthong, Xiaolin Xu:
VSALUT: A Lightweight Low-Dimensional VSA Classifier for Efficient Inference on FPGA. 119-123 - Xiaohan Gao, Zhili Xiong, Yusu Wang, David Z. Pan:
DiffRouter: A Differentiable Routing Framework for UltraScale FPGAs. 124-132 - Shashwat Shrivastava, Luka Kuresevic, Alexandros Poupakis, Chirag Ravishankar, Dinesh Gaitonde, Stefan Nikolic, Mirjana Stojilovic:
PathSteiner: Improving PathFinder with Quasi-Optimal Steiner-Tree Initialization. 133-141 - Yaozhang Liu:
Enabling Net-Level Global Vision in FPGA Routing via Precomputed Steiner Potential Fields. 142-150 - Faaiq G. Waqar, Matthew Chen, Zifan He, Zishen Wan, Minji Shon, Wei-Hsing Huang, Jason Cong, Shimeng Yu:
Enabling Context-Switchable Monolithic 3D FPGA Design Using Bistable Ferroelectric Inverters. 151-160 - Valentino Guerrini, Giuseppe Sorrentino, Alessandro Barenghi, Davide Conficconi:
ReFHE-NTT: Resource-Driven NTT FPGA Architecture for Fully Homomorphic Encryption. 161-170 - Jiayi Wang, Maohua Nie, Sin-Chen Lin, C.-J. Richard Shi, Ang Li:
TransDot: An Area-efficient Reconfigurable Floating-Point Unit for Trans-Precision Dot-Product Accumulation for FPGA AI Engines. 171-175 - Dimitrios Danopoulos, Enrico Lupi, Chang Sun, Sebastian Dittmeier, Michael Kagan, Vladimir Loncar, Maurizio Pierini:
AIE4ML: An End-to-End Framework for Compiling Neural Networks for the Next Generation of AMD AI Engines. 176-184 - Jason Kimko, Jason Cong:
When Systolic Arrays Meet AI Engines: Architectural Constraints on AMD Versal ACAP. 185-193 - Giuseppe Sorrentino, Paolo Salvatore Galfano, Claudio Di Salvo, Eleonora D'Arnese, Davide Conficconi:
Adaptive AIE-PL Systems for Efficient End-to-End Pyramidal 3D Image Registration. 194-203 - Hailiang Hu, Haodong Chang, Donghao Fang, Zhenrui Wang, Wuxi Li, Rongjian Liang, Bo Yuan, Jiang Hu:
LegoMap: Optimization for High-Throughput Transformer Computing on AI Engine-Based FPGAs. 204-212 - Damien Simon, Olivier Sentieys, Sylvain Lefebvre:
Hardware Stencil Accelerator with Periodic Boundary Conditions. 213-221 - Tianyou Bao, Joshua Ennis, Kirill Morozov, Jiafeng Xie:
Trident: Efficient FPGA Acceleration of XMSS Tree in Post-Quantum Signature Scheme SLH-DSA. 222-230 - Jebacyril Arockiaraj, Dhruv Parikh, Viktor K. Prasanna:
ImageHD: Energy-Efficient On-Device Continual Learning of Visual Representations via Hyperdimensional Computing. 231-240 - Sachini Wickramasinghe, Cauligi S. Raghavendra, Viktor K. Prasanna:
FASTR: FPGA-based Acceleration of Hierarchical Foundation Models for SAR ATR. 241-250 - Sunjae Kim, Gwanhong Park, Jeawoo Lim, Faaiz Asim, Jongeun Lee:
AccelOrb: FPGA Acceleration of Orb v2 for Fast Molecular Dynamics. 251-255 - Jihui Qi, Yongjiang Xue, Qingzeng Song:
HESP-Stream: A Sensor-Direct, Instruction-Driven FPGA System for Real-Time Sparse Event Processing. 256 - Xiaofeng Zhou, Linfeng Du, Guangyu Hu, Sharad Sinha, Hongce Zhang, Wei Zhang:
AutoINV: Automated Invariant Generation Framework for Formal Verification on High-Level Synthesis Designs. 257 - Yufeng Luo, Peikun Hong, Jing Wang, Feiyang Wu, Chao Li, Minyi Guo:
LiveGraph: High-Performance On-FPGA Dynamic Graph Updating Framework. 258 - Kaustubh Manohar Mhatre, Vedant Tewari, Aditya Ray, Farhan Khan, Ridwan Olabiyi, Ashif Iquebal, Aman Arora:
Accelerating Topology Optimization on AMD Versal AIE-ML Engines. 259 - Melisande Zonta-Roudes, Nora Hinderling, Supraja Sridhara, Srinidhi Nagendra, Shweta Shinde:
LLM-Assisted Analysis of On-Chip Protocol Implementations. 260 - Shuxuan Li, Nikela Papadopoulou, Wim Vanderbauwhede:
A Streaming FPGA Architecture for Sparse Matrix Multiplication with Sparsity-Aware Data Reordering. 261 - Victor J. B. Jung, Gagandeep Singh, Joseph Melber, Kristof Denolf, Francesco Conti, Luca Benini:
STEEL: Sparsity-Aware Fused Attention for Energy-Efficient Long-Sequence Inference on AMD's XDNA™ NPU. 262 - Gabriel Rodriguez-Canal, Nick Brown, Maurice Jamieson, Nicolas Bohm Agostini, Ankur Limaye, Vito Giovanni Castellana, Joseph B. Manzano, Antonino Tumeo:
Towards Compiler-Driven Dynamic Partial Reconfiguration with MLIR. 263 - Yanlong Huang, Jierui Liu, Yuhan She, Rongliang Fu, Tsung-Yi Ho, Hong Yan, Ray C. C. Cheung:
Chariot: Compiler-Aware Heterogeneous Graph Representation Learning for Automated HLS Optimization. 264 - Wei-Cheng Zeng, Kuan-Ting Lai:
DTCore: A Compiler-Directed Control-Minimal FPGA Compute Engine. 265 - Thomas Bain, David B. Thomas, Graeme M. Bragg:
Utilising Pipelined Buses to Provide Resource Efficient Dynamic Thread Scheduling in Barrel Scheduled Processors. 266 - Yiwei Wang, Chang Wu:
Design Space Exploration for Layer Pipelined DNN Accelerators Based on FPGAs. 267 - Ruihong Yin, Yue Zheng, Chaohui Li, Ahmet Efe, Abhimanyu Kumar, Ziqing Zeng, Ulya R. Karpuzcu, Sachin S. Sapatnekar, Chris H. Kim:
A Hybrid Ising FPGA-COBI Architecture with Hardware-Based Problem Decomposition. 268-269 - Shwet Chitnis, Fergus Xu, Ayush Kulkarni, Jiayi Wang, Jingqun Zhang, Arjun Raje, Ang Li:
Precision-aware Communication in CGRAs. 269 - Filip Wojcicki, Omar Sharif, Ebby Samson, Paul H. J. Kelly, George A. Constantinides, Christos Bouganis, Wayne Luk:
Towards Small Language Models on FPGAs. 270 - Jiarun Yan, Ao Liu, Si Zhang, Congwu Zhang, Yazhou Wang, Shiqi Liu, Ke Zhang:
SCOPE: SCalable and Observable PEripheral-Borrowing Framework for FPGA-Based Prototyping. 271 - Yujie Yan, Guanhua Chen, Keren Zhu:
LENS-HLS: LLM-Enhanced Learning-based Design Space Exploration for High-Level Synthesis. 272 - Andy Wanna, Hanqiu Chen, Cong Callie Hao:
ForgeBench: A Machine Learning Benchmark Suite and Auto-Generation Framework for Next-Generation HLS Tools. 273 - Yazhe Zhang, Shouyu Du, Zhenyu Xu, Miaoxiang Yu, Dingjiang Yan, Zhiheng Ni, Qing Yang, Tao Wei:
An Efficient Dataflow Framework for DiT-Based Image Generation. 274 - Xingzhen Chen, Zhuoping Yang, Jinming Zhuang, Shixin Ji, Sarah Schultz, Zheng Dong, Weisong Shi, Peipei Zhou:
DORA: Dataflow-Instruction Orchestration Architecture for DNN Acceleration. 275 - Kai Shao, Erwei Wang, He Li:
HAMG: A Hierarchical Automated MemTile-based GEMM Accelerator for Versal AIE-ML. 276 - Wesley Pang, Gregory Jun, Feiyang Liu, Deming Chen:
TileFuse: Fused Mixed-Precision Kernels for Quantized LLM Inference on AMD XDNA2 NPUs. 277 - Sharan Kumar, Sandesh Goyal, Srini Srinivasan, Aashish Tripathi:
Lightweight Lossless Compression Scheme for Video Applications on Versal ACAP Devices. 278 - Rakshith Jayanth, Viktor K. Prasanna:
FAST-Prefill: FPGA Accelerated Sparse Attention for Long Context LLM Prefill. 279 - Shashank Obla, Bin Li, James C. Hoe:
Lightweight Queueing Abstraction for Rapid Simulation and Automated Tuning of Input-Dependent Streaming Pipelines on FPGAs. 280 - Zhengyan Liu, Ce Guo, Zehuan Zhang, Qiang Liu, Wayne Luk:
EDSSC: An Efficient FPGA-based Accelerator for Dynamic Sparse Spectral Clustering. 281 - Sayanti Pal, Alexander Lehnert, Marc Reichenbach:
Combining HLS and Computation Coding for Balanced Matrix-Vector Engines on FPGA. 282 - Shadi Matinizadeh, Anup Das:
Sparse Compressed Quantized Dataflow Architecture (QUDA) for Neuromorphic Computing. 283 - Arun M, Madhav Rao:
Efficient Split-Posit DSP Slice Architecture for Embedded FPGA Fabrics. 284 - Guan-Wei Lai, Yi-Chen Hu, Chia-Yu Kuo, Wei-Chien Cheng, Yi-Chung Wu:
Reconfigurable Computing Challenge: A High-Throughput FPGA Accelerator for Real-Time 3D Gaussian Splatting. 285-288 - Marc Neu, Frank Baptist, Thomas Lobmaier, Fabio Papagno, Torben Ferber, Jürgen Becker:
Reconfigurable Computing Challenge: Real-Time Graph Neural Networks for Online Event Selection in Big Science. 289-293 - Xiaoyu Liang, Elaine Cao, Chun-Ning Kao, David Lin, Jiajie Li, Zhiru Zhang:
Reconfigurable Computing Challenge: Deploying SmolVLA Model on an AMD XDNA NPU. 294-298 - Jiayi Li, Hongxiao Zhao, Wenshuo Yue, Yihan Fu, Daijing Shi, Anjunyi Fan, Bonan Yan:
Reconfigurable Computing Challenge: FPGA-Gym-v2: FPGA-Based RL Environment Acceleration with LLM-Assisted Onboarding. 299-302 - Qiuping Wu, Mugeng Liu, Yixuan Zhang, Hongxiao Zhao, Yihan Fu, Gang Huang, Yun Ma, Bonan Yan:
Reconfigurable Computing Challenge: FPGA-Based WebAssembly Stack Co-Processor. 303-306 - Gram Koski, Sean Lipps, Zhenghua Ma, G. Abarajithan, Ryan Kastner:
Reconfigurable Computing Challenge: Transformer for Jet Tagging on Versal AI Engines. 307-310 - Shashank Obla, Tommy Tracy II, Matthew Beck, James C. Hoe, Kevin Skadron, Wajih Ul Hassan:
Reconfigurable Computing Challenge: RapidScan High-Throughput Parameterized HLS-based Streaming String Matching Library for FPGAs. 311-314 - Vyshnavi Alladi, Ronald Sass:
Impact of Ultra Ethernet Transport on Co-Tenant Latency in Reconfigurable Data Center NICs: A Simulation Study. 315-316 - Claudio Di Salvo, Davide Conficconi:
To Infinity and Beyond: A Reconfigurable Architecture for Space Vision Computing. 317-318 - Rishov Sarkar, Cong Callie Hao:
From Acceleration to Accelerating Acceleration: Applications and Tools for Democratizing Hardware Design. 319-320 - Giuseppe Sorrentino, Davide Conficconi:
Unleashing Heterogeneous Systems Capabilities to Enhance Compute-Intensive Workloads. 321-322
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