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ORCID40th DCIS 2025: Santander, Spain
- 40th Conference on Design of Circuits and Integrated Systems, DCIS 2025, Santander, Spain, November 26-28, 2025. IEEE 2025, ISBN 979-8-3315-8091-9
- Sara Alonso, Alejandro Arteaga
, Leire Muguira, Carlos Cuadrado, Aitzol Zuloaga, Jaime Jiménez, Jesús Lázaro, Jose Ignacio Garate, José Ángel Araujo, Victor Martínez, Unai Bidarte, Armando Astarloa:
A Proof-Of-Concept ASIC RISC-V Based SoC for Industrial Applications. 1-6 - David Cantero, Alexander Ugena, Laura Sanz, Alejandro Arteaga, Armando Astarloa:
Performance Analysis of Convolution Function for IA Edge Computing Acceleration Using a 32-bit RISC-V CPU Implementation. 7-12 - Román Cárdenas, Pedro Malagón, Patricia Arroba, Josué Pagán, José Manuel Moya:
RISCV-SLIC: Rust Software-Level Interrupt Controller for RISC-V Microcontrollers. 13-18 - Andrea Sannino, José Ignacio Artigas, Aránzazu Otín:
An Improved Discrete Time Amplifier-Less Potentiostat Architecture for Metabolic Sensing Applications. 19-24 - Michel Justino Bai, Iñigo Adin, Markos Losada:
Learning to Sense Sustainably: RL-Based Control for Solar-Powered IoT Nodes. 25-30 - Abel Reyes Cubas, David Galante Sempere, Javier del Pino, Sunil Lalchand Khemchandani:
A Built-In CMOS Temperature Sensor for On-Chip Thermal Monitoring from 0°C to 100°C with a 0.137°C of Innacuracy. 31-36 - Sergio Tejeda, Roberto Román, Rosario Arjona, Iluminada Baturone:
Electromagnetic Side-Channel Attack on a SoC-FPGA Fingerprint Recognition System. 37-42 - Erica Tena-Sánchez, Francisco Eugenio Potestad-Ordóñez, Miguel Martín-González, Alejandro Casado-Galán, Antonio J. Acosta:
Low Entropy Masking Protection Scheme for Ascon Cipher to Counteract Side-Channel Attacks. 43-48 - Carlos Fernández-García, Carmen Baena Oliva, Pilar Parra Fernández, Carlos Jesús Jiménez-Fernández:
A Lightweight AES Peripheral for RISC-V Cores and IoT Applications. 49-54 - Pilar Cano-Lozano, Enrique Personal, Diego Francisco Larios, Samuel Domínguez-Cid, Juán Ignacio Guerrero, Carlos León:
Electric Vehicle Emulator for Study as a Distributed Energy Resource. 55-60 - Santiago Murano, Martín Colombo, Carlos De Marziani, Rubén Nieto, Sofia Micaela Laskowski Orlandi:
FPGA Architectures for Reliable Transmission of Pre-Stored Acoustic Signals in Underwater Localization Systems. 61-66 - Fermin Esparza-Alfaro, Antonio J. López-Martín:
CMOS Micropower Current-Mode Sinh-Domain Filter with Multidecade Tuning. 67-71 - Óliver Pincelli Westin, Rafael Takeshi Inuoe, Anderson Aparecido Dionizio, Leonardo Poltronieri Sampaio, Sérgio Augusto Oliveira da Silva:
Improved Modified Zeta Inverter for Single-Phase Grid-Tied System. 72-77 - Marina Cordovilla, Pablo Sánchez, Andrés Martínez:
Efficient Neural Architectures for Acoustic Monitoring of Livestock. 78-83 - Rubén Padial-Allué, Alberto Martín-Martín, Encarnación Castillo, Uwe Meyer-Baese, Víctor Toral, Luis Parrilla, Antonio García:
1-D Convolutional Autoencoder for Fetal and Maternal ECG Classification Oriented to Hardware Implementation Acceleration. 84-89 - Jordi Fornt, Pau Fontova-Musté, Martí Caro, Jaume Abella, Josep Altet, Antonio Rubio, Francesc Moll:
Approximate Circuits Versus Quantization for Energy Efficient Deep Neural Networks. 90-95 - Josep L. Rosselló, Christiam F. Frasser, Arnau Salas-Barenys, Joan Cesari, Vincent Canals, Lluc Crespí-Castañer, Joan Font-Rosselló, Alejandro Morán, Miquel Roca:
A 1.12 TOPS/W 180 nm Stochastic Computing-Based Neuromorphic Circuit. 96-101 - Alejandro Morán, Lluc Crespí-Castañer, Christiam F. Frasser, Joan Font-Rosselló, Vincent Canals, Miquel Roca, Josep L. Rosselló:
A Comparative Analysis of Bipolar and Sign-Magnitude Stochastic Computing Approaches in Quantized Neural Networks. 102-107 - Dídac Llobet, Ioannis K. Chatzipaschalis, Antonio Calomarde, Antonio Rubio:
Character Recognition Application of a Neural Circuit Including Lateral Inhibitory Mechanisms. 108-113 - Prathamesh Satish Deshpande, Giovanni Grandi, Stephan Schoenfeldt, Fabian Lurz:
Full-Integer Spiking Neural Network Inference with RISC-V ISA Extensions for Radar-Based Gesture Recognition. 114-119 - Bernabé Linares-Barranco, Luis A. Camuñas-Mesa, Teresa Serrano-Gotarredona:
Three Decades of IMSE Neuromorphic Group. 120-125 - Cristina Bermúdez-Martín, Samuel López Asunción, Pablo Ituero:
Design Space Exploration of FPGA-Based Spiking Neural Networks for Angle of Arrival Detection. 126-131 - Markel Galarraga, Charles-Alexis Lefebvre, Jon Pérez-Cerrolaza, Jose A. Pascual:
Analyzing Linux System Call Variability: Real-Time Patch Impact and System Call Monitoring. 132-137 - Jose Luis Mira Serrano, Carlos Ernesto Hernandez Orellana, Jesús Barba Romero, Soledad Escolar Díaz, José Antonio de la Torre, Fernando Rincón Calle:
Exploring Design Spaces in Embedded Systems: An Approach Based on Genetic Programming, Particle Swarm and Reinforcement Learning. 138-143 - Eduardo Tomasi, César Fuguet, Christian Fabre, Frédéric Pétrot:
HPC Workload Analysis Using Distributed Cross-ISA Binary Instrumentation. 144-149 - Daniel Suárez, Pedro Hernández-Fernández, Víctor Fernández, Gustavo M. Callicó:
Video Action Recognition in SoC FPGAs Driven by Neural Architecture Search. 150-155 - Jaime Sancho, Manuel Villa, Gonzalo Rosa-Olmeda, Alejandro Martinez de Ternero, Miguel Chavarrías, Eduardo Juárez, César Sanz:
Deep Learning-Based Depth Estimation for Facial Morphology Characterization in Neurosurgery Applications. 156-161 - F. D. Suárez Bonilla, José M. de la Rosa, Gustavo Liñán Cembrano:
Multi-Domain Feature Extraction for ML-Based Over-the-Air RF Signal Classification. 162-167 - Amadeo de Gracia Herranz, Borja Gutiérrez De Cabiedes, Javier De Mena Pacheco, Marisa López-Vallejo:
Ultra-Narrow Current Pulses Measurement Using a Cost-Effective Instrumentation System. 168-171 - Juan Luis Soler-Fernández, Ángel Diéguez, Joan Daniel Prades, Oscar Alonso:
Sub-nW Thyristor Based Wake-Up Timer for Low Duty Cycle Ioct Sensing Applications. 172-176 - Chih-Feng Wu, Bo-An Lin, Chi-Tien Sun:
A 4 × 4 K-Best Spatial Modulation MIMO Detection for Visible Light Communication Systems. 177-181 - Muhammad Umer Khalid, Trond Ytterdal, Snorre Aunet:
Comparative Analysis of Full Adders Based on DTMOS Schmitt-Trigger Standard Cells Operating at Sub-100 mV Supply Voltage. 182-187 - Mehdi Shahabi, Andoni Beriain, Noemí Perez:
A 65 nm CMOS Ultra-Low-Quiescent-Current On-Chip PMIC for Energy-Limited Harvesting Systems. 188-196 - M. Clara Simões, Floriberto Lima, Marcelino B. Santos, Fábio Passos:
A 300 mA Fully-Integrated Inverter-Based LDO with Enhanced Supply Insensitivity for Smart Edge AI Applications. 194-198 - Francisco Albertuz, Mario Garrido:
Hardware-Efficient Gaussian and Sobel Filters for Real-Time Image Processing on FPGA. 199-204 - Lluís Ribas-Xirgo:
Hardware Implementation of the Hungarian Algorithm for Optimum Task Assignments. 205-210 - Pablo Hormigo-Jiménez, Javier Hormigo:
Configurable Ultra-High-Throughput QRD FPGA Accelerators for Small Matrices. 211-216 - Rubén Nieto, Silvia Iniesta, Santiago Murano, Pedro Rafael Fernández, Susana Borromeo:
FPGA-Based Implementation of sEMG Feature Extraction and Movement Classification with MLP. 217-222 - Uxua Esteban-Eraso, Gesler Ramos, Santiago Celma, Francisco José Torcal-Milla, Carlos Sánchez-Azqueta:
Design of a CMOS Transmitter Chain for Satellite on the Move Communications. 223-227 - Alvaro Urain, David del Rio, Andoni Beriain, Héctor Solar, Aleksei Nerushenko, Roc Berenguer:
Design of a 160-210 GHz SiGe HBT Square-Law Detector for Total Power Radiometers. 228-232 - F. Bonfiglio-Buendía, Natalia A. Fernandez-Garcia, Paula López, Víctor M. Brea, Diego Cabello:
CMOS SPDT Switch Topologies in the Frequency Range of 6 to 20 GHz. 233-238 - Juan Gallego, José Pedro Ferreira, Luís Alves, Daniel Vázquez, João Bispo, Alfonso Rodríguez, Nuno Paulino, Andrés Otero:
Acceleration of C/C++ Kernels and ONNX Models on CGRAs with MLIR-Based Compilation. 239-244 - Maryam Katebzadeh, Daniel Vázquez, Andrés Otero, Alfonso Rodríguez:
A Framework for Automated CGRA Design Space Exploration with Genetic Algorithm Optimization. 245-250 - Aleksei Nerushenko, Roc Berenguer, Alvaro Urain, Héctor Solar:
A 1.15 mW SiGe BiCMOS Cryogenic LNA for Superconducting Qubit Readout with 4.5 K Noise Temperature From 4 to 9 GHz. 251-255 - Ainhoa Leal, Luis Montal, Aleksei Nerushenko, Héctor Solar, Roc Berenguer:
A Methodology for Cryogenic Modeling of CMOS Technology Based on BSIM-BULK. 256-261 - Muhammad Umer Khalid, Trond Ytterdal, Snorre Aunet:
Robust DTMOS Schmitt-Trigger Circuits in 130 nm SOI CMOS for Sub-100mV Supply Voltage. 262-267 - Tom Bergmann, Joel Damiens, Alfonso Hildebrand Rueda, Stephane Lacouture, Remy Cellier, Nacer Abouchi:
A Programmable, Negative, and Dynamically Biased Sampler for Ultra-Low Power Body-Bias Generators in 18nm FD-SOI. 268-273
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