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ORCIDDASIP 2010: Edinburgh, Scotland, UK
- Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, DASIP 2010, Edinburgh, Scotland, UK, October 26-28, 2010, Electronic Chips & Systems design Initiative, ECSI. IEEE 2010, ISBN 978-1-4244-8735-6
- Hongzhi Liu, Neil W. Bergmann
:
An FPGA softcore based implementation of a bird call recognition system for sensor networks. 1-6 - Wim Vanderbauwhede, Syed Waqar Nabi:
A high-level language for programming a NoC-based Dynamic Reconfiguration Infrastructure. 7-14 - Erik Markert, Enrico Billich, Claudia Tischendorf, Uwe Proß, Thilo Leibelt, Ulrich Heinkel, Joachim Knäblein, Axel Schneider:
An in-band reconfigurable network node based on a heterogeneous platform. 15-20 - Santosh Ghosh, Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury:
High speed Fp multipliers and adders on FPGA platform. 21-26 - Yangyang Tang, Emmanuel Boutillon, Christophe Jégo, Michel Jézéquel:
A new single-error correction scheme based on self-diagnosis residue number arithmetic. 27-33 - Jia Huang, Andreas Raabe, Christian Buckl, Alois C. Knoll:
Runtime adaptive allocation of dynamically mixed tasks on a heterogeneous MPSoC platform. 34-41 - Mickael Lanoe, Eric Senn:
Energy modeling of the virtual memory subsystem for real-time embedded systems. 42-47 - Arnaud Dion, Emmanuel Boutillon, Vincent Calmettes, Emmanuel Liegon:
A flexible implementation of a Global Navigation Satellite System (GNSS) receiver for on-board satellite navigation. 48-53 - Antoine Courtay, Alain Pegatoquet, Michel Auguin, Chiraz Chaabane:
Wireless Sensor Network node global energy consumption modeling. 54-61 - Robert Hartmann, Fadi Al Machot, Philipp Mahr, Christophe Bobda:
Camera-based system for tracking and position estimation of humans. 62-67 - Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser:
Designing dynamically reconfigurable SoCs: From UML MARTE models to automatic code generation. 68-75 - Khodor Ahmad Fawaz, Tughrul Arslan, Sami Khawam, Mark Muir, Ioannis Nousias, Iain Lindsay, Ahmet T. Erdogan:
A dynamically reconfigurable asynchronous processor for low power applications. 76-83 - Xin Zhao, Ahmet T. Erdogan, Tughrul Arslan:
A hybrid dual-core Reconfigurable Processor for EBCOT tier-1 encoder in JPEG2000 on next generation of digital cameras. 84-89 - Sébastien Courroux, Stéphane Guyetant, Stéphane Chevobbe, Michel Paindavoine:
A wavelet-based demosaicking algorithm for embedded applications. 90-96 - Etienne Faure, Gabriel Marchesan Almeida, Mounir Benabdenbi, Pascal Benoit, Fabien Clermidy, François Pêcheux, Gilles Sassatelli, Lionel Torres:
An in-memory monitoring database for self adaptive MP2SoCs. 97-104 - Benoît Miramond, Liliana Cucu-Grosjean:
Generation of static tables in embedded memory with dense scheduling. 105-112 - Nicolas Siret, Matthieu Wipliez, Jean-François Nezan, Aimad Rhatay:
Hardware code generation from dataflow programs. 113-120 - Virginie Fresse, Dominique Houzet, Christophe Gravier:
GPU architecture evaluation for multispectral and hyperspectral image analysis. 121-127 - Andrei Banciu, Emmanuel Casseau, Daniel Ménard, Thierry Michel:
A case study of the stochastic modeling approach for range estimation. 128-135 - Muhammad Khurram Bhatti, Cécile Belleudy, Michel Auguin:
An inter-task real time DVFS scheme for multiprocessor embedded systems. 136-143 - Francesca Palumbo, Danilo Pani, Emanuele Manca, Luigi Raffo, Marco Mattavelli, Ghislain Roquier:
RVC: A multi-decoder CAL Composer tool. 144-151 - Cecile Beaumin, Olivier Sentieys, Emmanuel Casseau, Arnaud Carer:
A coarse-grain reconfigurable hardware architecture for RVC-CAL-based design. 152-159 - Maitane Barrenechea, Luis G. Barbero, Mikel Mendicute, John S. Thompson:
Design and hardware implementation of a low-complexity multiuser vector precoder. 160-167 - Erwan Raffin, Christophe Wolinski, François Charot, Krzysztof Kuchcinski, Stéphane Guyetant, Stéphane Chevobbe, Emmanuel Casseau:
Scheduling, binding and routing system for a run-time reconfigurable operator based multimedia architecture. 168-175 - Fadoua Guezzi Messaoud, Arnaud Peizerat, Antoine Dupret, Yves Blanchard:
On-chip compression for HDR image sensors. 176-182 - Jérôme Gorin, Matthieu Wipliez, Françoise J. Prêteux, Mickaël Raulet:
A portable Video Tool Library for MPEG Reconfigurable Video Coding using LLVM representation. 183-190 - Christophe Lucarz, Ghislain Roquier, Marco Mattavelli:
High level design space exploration of RVC codec specifications for multi-core heterogeneous platforms. 191-198 - João G. P. Rodrigues, João Canas Ferreira:
FPGA-based rectification of stereo images. 199-206 - Endri Bezati, Marco Mattavelli, Mickaël Raulet:
RVC-CAL dataflow implementations of MPEG AVC/H.264 CABAC decoding. 207-213 - Denis Dessales, Anne-Marie Poussard, Rodolphe Vauzelle, Noël Richard, François Gaudaire, Christophe Martinsons:
Physical layer study in a goal of robustness and energy efficiency for wireless sensor networks. 214-221 - Anis Rahman, Dominique Houzet, Denis Pellerin, Lionel Agud:
GPU implementation of motion estimation for visual saliency. 222-227 - Antoine Eiche, Daniel Chillet, Sébastien Pillement, Olivier Sentieys:
Task placement for dynamic and partial reconfigurable architecture. 228-234 - Ana Pinzari, Mohamed Shawky:
Characterization of capture actions in video sequences. 235-241 - Tiago Dias, Nuno Roma, Leonel Sousa:
Hardware/software co-design of H.264/AVC encoders for multi-core embedded systems. 242-249 - Mario Alberto Ibarra-Manzano, Michel Devy, Jean-Louis Boizard:
Real-time classification based on color and texture attributes on an FPGA-based architecture. 250-257 - Zulhakimi Razak, Ahmet T. Erdogan, Tughrul Arslan:
Low power noise detection circuit utilizing switching activity measurement method. 258-264 - Ruirui Gu, Jonathan Piat, Mickaël Raulet, Jörn W. Janneck, Shuvra S. Bhattacharyya:
Automated generation of an efficient MPEG-4 Reconfigurable Video Coding decoder implementation. 265-272 - Bertrand Rousseau, Philippe Manet, Igor Loiselle, Jean-Didier Legat, Hans Vandierendonck:
A methodology for precise comparisons of processor core architectures for homogeneous many-core DSP platforms. 273-280 - Stéphane Chevobbe, Suresh Pajaniradja, Laurent Letellier:
Exploration platform of embedded simd architecture for autonomous retinas. 281-288 - Xin Zhao, Ying Yi, Ahmet T. Erdogan, Tughrul Arslan:
Dual-core reconfigurable demosaicing engine for next generation of portable camera systems. 289-294 - Martin Zlatanski, Wilfried Uhring, Virginie Zint, Jean-Pierre Le Normand, Daniel Mathiot:
Architectures and signal reconstruction methods for nanosecond resolution Integrated Streak Camera in standard CMOS technology. 295-302 - Matthieu Wipliez, Mickaël Raulet:
Classification and transformation of dynamic dataflow programs. 303-310 - Xabier Iturbe, Khaled Benkrid, Tughrul Arslan, Imanol Martinez, Mikel Azkarate-askasua, Marco D. Santambrogio:
A Roadmap for Autonomous Fault-Tolerant Systems. 311-321
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