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ORCID15th COOL Chips 2012: Yokohama, Japan
- Hiroaki Kobayashi, Makoto Ikeda, Fumio Arakawa:
2012 IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips XV, Yokohama, Japan, April 18-20, 2012. IEEE Computer Society 2012, ISBN 978-1-4673-1201-1 - Jinwook Oh, Gyeonghoon Kim, Junyoung Park, Injoon Hong, Seungjin Lee, Joo-Young Kim, Hoi-Jun Yoo:
A simultaneous multithreading heterogeneous object recognition processor with machine learning based dynamic resource management. 1-3 - Tse-Wei Chen, Makoto Ikeda:
Dual-stage hardware architecture of on-line clustering with high-throughput parallel divider for low-power signal processing. 1-3 - Koji Hashimoto:
Poster preface. 1-2 - Yasuhisa Shimazaki, Noriyuki Miura, Tadahiro Kuroda:
A 5.184Gbps/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processors. 1-3 - Yukoh Matsumoto, Tomoyuki Morimoto, Michiya Hagimoto, Hiroyuki Uchida, Nobuyuki Hikichi, Fumito Imura, Hiroshi Nakagawa, Masahiro Aoyagi:
Cool System scalable 3-D stacked heterogeneous Multi-Core / Multi-Chip architecture for ultra low-power digital TV applications. 1-3 - Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada:
Gate-level process variation offset technique by using dual voltage supplies to achieve near-threshold energy efficient operation. 1-3 - Toshiyuki Yamagishi, Tatsuo Shiozawa, Koji Horisaki, Hiroyuki Hara, Yasuo Unekawa:
An area-efficient, standard-cell based on-chip NMOS and PMOS performance monitor for process variability compensation. 1-3 - Weihan Wang, Yuya Ohta, Yoshifumi Ishii, Kimiyoshi Usami, Hideharu Amano:
Trade-off analysis of fine-grained power gating methods for functional units in a CPU. 1-3 - Ye Gao, Naoki Shoji, Ryusuke Egawa, Hiroyuki Takizawa
, Hiroaki Kobayashi:
A media-oriented vector architectural extension with a high bandwidth cache system. 1-3 - Kazutoshi Suito, Kei Fujii, Hiroki Matsutani, Nobuyuki Yamasaki:
Dependable Responsive Multithreaded Processor for distributed real-time systems. 1-3
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