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ORCID28th Asian Test Symposium 2019: Kolkata, India
- 28th IEEE Asian Test Symposium, ATS 2019, Kolkata, India, December 10-13, 2019. IEEE 2019, ISBN 978-1-7281-2695-1
Session A1: AI Methods
- Cheng-Hung Wu, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Gaurav Veda, Sudhakar M. Reddy, Chun-Cheng Hu, Chong-Siao Ye
:
Deep Learning Based Test Compression Analyzer. 1-6 - Elbruz Ozen, Alex Orailoglu:
Sanity-Check: Boosting the Reliability of Safety-Critical Deep Neural Network Applications. 7-12 - Spencer K. Millican, Yang Sun, Soham Roy, Vishwani D. Agrawal:
Applying Neural Networks to Delay Fault Testing: Test Point Insertion and Random Circuit Training. 13-18
Session A2: ATPG/BIST
- Naixing Wang, Chen Wang, Kun-Han Tsai, Wu-Tung Cheng, Xijiang Lin, Mark Kassab, Irith Pomeranz:
TEA: A Test Generation Algorithm for Designs with Timing Exceptions. 19-24 - Manobendra Nath Mondal, Animesh Basak Chowdhury, Manjari Pradhan, Susmita Sur-Kolay, Bhargab B. Bhattacharya:
Fault Coverage of a Test Set on Structure-Preserving Siblings of a Circuit-Under-Test. 25-30 - Yushiro Hiramoto, Satoshi Ohtake, Hiroshi Takahashi:
A Built-In Self-Diagnostic Mechanism for Delay Faults Based on Self-Generation of Expected Signatures. 31-36
Session A3: Testing AI Chips
- Tsung-Chu Huang:
Self-Checking Residue Number System for Low-Power Reliable Neural Network. 37-42 - Aibin Yan, Zhen Wu, Lu Lu, Zhili Chen, Jie Song, Zuobin Ying, Patrick Girard, Xiaoqing Wen:
Novel Radiation Hardened Latch Design with Cost-Effectiveness for Safety-Critical Terrestrial Applications. 43-48 - Saranyu Chattopadhyay, Preeti Kumari, Biswajit Ray, Rajat Subhra Chakraborty:
Machine Learning Assisted Accurate Estimation of Usage Duration and Manufacturer for Recycled and Counterfeit Flash Memory Detection. 49-54 - Aibin Yan, Zhen Wu, Jun Zhou, Yuanjie Hu, Yan Chen, Zuobin Ying, Xiaoqing Wen, Patrick Girard:
Design of a Sextuple Cross-Coupled SRAM Cell with Optimized Access Operations for Highly Reliable Terrestrial Applications. 55-60 - Aditya Rohan, Kanad Basu, Ramesh Karri:
Can Monitoring System State + Counting Custom Instruction Sequences Aid Malware Detection? 61-66
Session A4: Test & BIST
- Ching-Yuan Chen, Jiun-Lang Huang:
Reinforcement-Learning-Based Test Program Generation for Software-Based Self-Test. 73-78 - Avishek Choudhury, Brototi Mondal, Biplab K. Sikdar:
Latency Aware Fault Tolerant Cache in Multicore Using Dynamic Remapping Clusters. 79
Session C4: Security Special
- Vinay B. Y. Kumar, Suman Deb, Rupesh Kumar, Mustafa Khairallah, Anupam Chattopadhyay, Avi Mendelson:
Recruiting Fault Tolerance Techniques for Microprocessor Security. 80-85 - Anirban Chakraborty, Manaar Alam, Debdeep Mukhopadhyay:
Deep Learning Based Diagnostics for Rowhammer Protection of DRAM Chips. 86-91 - Sujit Kumar Muduli, Pramod Subramanyan:
Towards Verifiably Secure Systems-on-Chip Platforms. 92-97 - Hau Sim Choo, Chia Yee Ooi, Michiko Inoue, Nordinah Ismail, Mehrdad Moghbel, Sreedharan Baskara Dass, Chee Hoo Kok, Fawnizu Azmadi Hussin:
Machine-Learning-Based Multiple Abstraction-Level Detection of Hardware Trojan Inserted at Register-Transfer Level. 98
Session A5: SOC Test
- Binod Kumar, Atul Kumar Bhosale, Masahiro Fujita, Virendra Singh:
Validating Multi-Processor Cache Coherence Mechanisms under Diminished Observability. 99-104
Session B5: Security
- Chee Hoo Kok, Chia Yee Ooi, Michiko Inoue, Mehrdad Moghbel, Sreedharan Baskara Dass, Hau Sim Choo, Nordinah Ismail, Fawnizu Azmadi Hussin:
Net Classification Based on Testability and Netlist Structural Features for Hardware Trojan Detection. 105-110 - Renjie Lu, Haihua Shen, Yu Su, Huawei Li, Xiaowei Li:
GramsDet: Hardware Trojan Detection Based on Recurrent Neural Network. 111-116 - Leandro Santiago de Araújo, Vinay C. Patil, Leandro Augusto Justen Marzulo, Felipe Maia Galvão França, Sandip Kundu:
Efficient Testing of Physically Unclonable Functions for Uniqueness. 117-122
Session A6: Verification
- Vineesh V. S., Binod Kumar, Rushikesh Shinde, Akshay Jaiswal, Harsh Bhargava, Virendra Singh:
Orion: A Technique to Prune State Space Search Directions for Guidance-Based Formal Verification. 123-128 - Felipe Augusto da Silva, Ahmet Cagri Bagbaba, Said Hamdioui, Christian Sauer:
Combining Fault Analysis Technologies for ISO26262 Functional Safety Verification. 129-134
Session B6: Analog Test
- Sayandeep Sanyal, Amit Patra, Pallab Dasgupta, Mayukh Bhattacharya:
A Structured Approach for Rapid Identification of Fault-Sensitive Nets in Analog Circuits. 135-140 - Md Imran Momtaz, Abhijit Chatterjee:
Hierarchical State Space Checks for Errors in Sensors, Actuators and Control of Nonlinear Systems: Diagnosis and Compensation. 141-146
Emerging Technologies
- Sourav Ghosh, Dolan Maity, Arijit Chowdhury, Surajit Kumar Roy, Chandan Giri:
Iterative Parallel Test to Detect and Diagnose Multiple Defects for Digital Microfluidic Biochip. 147-152 - Arighna Deb, Debesh K. Das:
Detailed Fault Model for Physical Quantum Circuits. 153-158 - Rolf Drechsler, Daniel Große:
Ensuring Correctness of Next Generation Devices: From Reconfigurable to Self-Learning Systems. 159-164
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