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ORCID24th Asian Test Symposium 2015: Mumbai, India
- 24th IEEE Asian Test Symposium, ATS 2015, Mumbai, India, November 22-25, 2015. IEEE Computer Society 2015, ISBN 978-1-4673-9739-1
1A: Power Aware Testing
- Sungyoul Seo, Yong Lee, Hyeonchan Lim, Joohwan Lee, Hongbom Yoo, Yojoung Kim, Sungho Kang:
Scan Chain Reordering-Aware X-Filling and Stitching for Scan Shift Power Reduction. 1-6 - Zhou Jiang, Dong Xiang, Kele Shen:
A Novel Scan Segmentation Design for Power Controllability and Reduction in At-Speed Test. 7-12 - Masayoshi Yoshimura, Yoshiyasu Takahashi, Hiroshi Yamazaki, Toshinori Hosokawa:
A Don't Care Filling Method to Reduce Capture Power Based on Correlation of FF Transitions. 13-18
1B: New DFT Approaches
- Grzegorz Mrugalski, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer
, Chen Wang:
TestExpress - New Time-Effective Scan-Based Deterministic Test Paradigm. 19-24 - Satyadev Ahlawat, Jaynarayan T. Tudu, Anzhela Yu. Matrosova, Virendra Singh:
A New Scan Flip Flop Design to Eliminate Performance Penalty of Scan. 25-30
2A: Test Generation
- Masahiro Fujita:
Detection of test Patterns with Unreachable States through Efficient Inductive-Invariant Identification. 31-36 - Tetsuya Masuda, Jun Nishimaki, Toshinori Hosokawa, Hideo Fujiwara:
A Test Generation Method for Data Paths Using Easily Testable Functional Time Expansion Models and Controller Augmentation. 37-42 - Chun-Hao Chang, Kuen-Wei Yeh, Jiun-Lang Huang, Laung-Terng Wang:
SDC-TPG: A Deterministic Zero-Inflation Parallel Test Pattern Generator. 43-48
2B: Memory Test and Repair
- Shyue-Kung Lu, Cheng-Ju Tsai, Masaki Hashizume:
Integration of Hard Repair Techniques with ECC for Enhancing Fabrication Yield and Reliability of Embedded Memories. 49-54 - Guopei Liu, Ying Wang, Sen Li, Huawei Li, Xiaowei Li:
A Lightweight Timing Channel Protection for Shared Memory Controllers. 55-60 - Josef Kinseher, Leonardo Bonet Zordan, Ilia Polian:
On the Use of Assist Circuits for Improved Coupling Fault Detection in SRAMs. 61-66 - Che-Wei Chou, Yong-Xiao Chen, Jin-Fu Li:
Testing Inter-Word Coupling Faults of Wide I/O DRAMs. 67-72
3A: Testing 3D Structures
- Rajit Karmakar, Aditya Agarwal, Santanu Chattopadhyay:
Test Infrastructure Development and Test Scheduling of 3D-Stacked ICs under Resource and Power Constraints. 73-78 - Konstantin Shibin, Vivek Chickermane, Brion L. Keller, Christos Papameletis, Erik Jan Marinissen:
At-Speed Testing of Inter-Die Connections of 3D-SICs in the Presence of Shore Logic. 79-84 - Jun Zhou, Huawei Li, Tiancheng Wang, Sen Li, Ying Wang, Xiaowei Li:
TWiN: A Turn-Guided Reliable Routing Scheme for Wireless 3D NoCs. 85-90
3B: Standards Test and Security
- Hejia Liu, Vishwani D. Agrawal:
Securing IEEE 1687-2014 Standard Instrumentation Access by LFSR Key. 91-96
4A: Timing and Delay Test
- Xijiang Lin, Wu-Tung Cheng, Janusz Rajski:
On Improving Transition Test Set Quality to Detect CMOS Transistor Stuck-Open Faults. 97-102 - Koji Asada, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara, Michael A. Kochte, Eric Schneider, Hans-Joachim Wunderlich, Jun Qian:
Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch. 103-108 - Matthias Kampmann, Michael A. Kochte, Eric Schneider, Thomas Indlekofer, Sybille Hellebrand, Hans-Joachim Wunderlich:
Optimized Selection of Frequencies for Faster-Than-at-Speed Test. 109-114 - Virendra Singh, Adit D. Singh, Kewal K. Saluja:
A Methodology for Identifying High Timing Variability Paths in Complex Designs. 115-120
4B: Circuits for Security and Resilience
- Dooyoung Kim, Muhammad Adil Ansari, Jihun Jung, Sungju Park:
Scan-Puf: Puf Elements Selection Methods for Viable IC Identification. 121-126 - Sabyasachi Deyati, Barry John Muldrey, Adit D. Singh, Abhijit Chatterjee:
Challenge Engineering and Design of Analog Push Pull Amplifier Based Physically Unclonable Function for Hardware Security. 127-132 - Adithyalal P. M, Shankar Balachandran, Virendra Singh:
A Soft Error Resilient Low Leakage SRAM Cell Design. 133-138 - Yuta Kimi, Go Matsukawa, Shuhei Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Analysis of Soft Error Propagation Considering Masking Effects on Re-Convergent Path. 139-144
5A: Test and Diagnosis
- Tino Flenker, André Sülflow, Görschwin Fey:
Diagnostic Tests and Diagnosis for Delay Faults Using Path Segmentation. 145-150 - Srinivasa Shashank Nuthakki, Santanu Chattopadhyay:
An Integrated Approach for Improving Compression and Diagnostic Properties of Test Sets. 151-156 - Michael A. Kochte, Atefe Dalirsani, Andrea Bernabei, Martin Omaña, Cecilia Metra, Hans-Joachim Wunderlich:
Intermittent and Transient Fault Diagnosis on Sparse Code Signatures. 157-162
5B: Resilient System Design and Test
- Sukrat Gupta, Neel Gala, G. S. Madhusudan, V. Kamakoti:
SHAKTI-F: A Fault Tolerant Microprocessor Architecture. 163-168 - Swagata Mandal, Suman Sau, Amlan Chakrabarti, Sushanta Kumar Pal, Subhasish Chattopadhyay:
FPGA Implementation of High Speed Latency Optimized Optical Communication System Based on Orthogonal Concatenated Code. 169-174 - V. Prasanth, Rubin A. Parekhji, Bharadwaj S. Amrutur:
Improved Methods for Accurate Safety Analysis of Real-Life Systems. 175-180
6A: Testing in FINFET and Emerging Technologies
- Kuan-Ying Chiang, Yu-Hao Ho, Yo-Wei Chen, Cheng-Sheng Pan, James Chien-Mo Li:
Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits. 181-186 - Ashwin Chintaluri, Abhinav Parihar, Suriyaprakash Natarajan, Helia Naeimi, Arijit Raychowdhury:
A Model Study of Defects and Faults in Embedded Spin Transfer Torque (STT) MRAM Arrays. 187-192
6B: Design Analysis, Verification and Validation
- Masahiro Ishida, Toru Nakura, Akira Matsukawa, Rimon Ikeno, Kunihiro Asada:
A Technique for Analyzing On-Chip Power Supply Impedance. 193-198 - Payman Behnam, Bijan Alizadeh:
In-Circuit Mutation-Based Automatic Correction of Certain Design Errors Using SAT Mechanisms. 199-204 - Saikat Dutta, Soumi Chattopadhyay, Ansuman Banerjee, Pallab Dasgupta:
A New Approach for Minimal Environment Construction for Modular Property Verification. 205-210 - Riccardo Cantoro, Mehrdad Montazeri, Matteo Sonza Reorda, Farrokh Ghani Zadegan, Erik Larsson:
On the testability of IEEE 1687 networks. 211-216 - Joyati Mondal, Debesh K. Das, Bhargab B. Bhattacharya:
Design-for-testability in reversible logic circuits based on bit-swapping. 217-222
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