default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDASAP 2000: Boston, MA, USA
- 12th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2000), 10-12 July 2000, Boston, MA, USA. IEEE Computer Society 2000, ISBN 0-7695-0716-6
Keynote
- William S. Song:
High-Performance Front-End Embedded Signal Processors for Adaptive Sensor Arrays.
Video and Multimedia Processors
- Ruby B. Lee:
Subword Permutation Instructions for Two-Dimensional Multimedia Processing in MicroSIMD Architectures. 3-14 - Mladen Berekovic, Peter Pirsch, Thorsten Selinger, Kai-Immo Wels, Carolina Miro, Anne Lafage, Christoph Heer, Giovanni Ghigo:
Architecture of an Image Rendering Co-Processor for MPEG-4 Systems. 15-24 - Wael M. Badawy
, Magdy A. Bayoumi:
A Multiplication-Free Parallel Architecture for Affine Transformation. 25-34 - Marco Antonio Dal Poz, Jose Edinson Aedo Cobo, Wilhelmus A. M. Van Noije, Marcelo Knörich Zuffo:
A Simple RISC Microprocessor Core Designed for Digital Set-Top-Box Applications. 35-
Reconfigurable Computing
- Sergej Sawitzki, Rainer G. Spallek, Jens Schönherr, Bernd Straube:
Formal Verification for Microprocessors with Extendable Instruction Set. 47-55 - Robert Rinker, Jeffrey Hammes, Walid A. Najjar, A. P. Wim Böhm, Bruce A. Draper:
Compiling Image Processing Applications to Reconfigurable Hardware. 56-65 - Holger Blume, Hans-Martin Blüthgen, Christiane Henning, Patrick Osterloh:
Integration of High-Performance ASICs into Reconfigurable Systems Providing Additional Multimedia Functionality. 66-
Modeling and Synthesis
- Ed F. Deprettere, Edwin Rijpkema, Paul Lieverse, Bart Kienhuis:
High Level Modeling for Parallel Executions of Nested Loop Algorithms. 79-91 - Andrew Stone, Elias S. Manolakos:
Minimal Complexity Hierarchical Loop Representations of SFG Processors for Optimal High Level Synthesis. 92-102 - Wen-Tsong Shiue:
High Level Synthesis for Peak Power Minimization Using ILP. 103-112 - Robert Schreiber, Shail Aditya, B. Ramakrishna Rau, Vinod Kathail, Scott A. Mahlke, Santosh G. Abraham, Greg Snider:
High-Level Synthesis of Nonprogrammable Hardware Accelerators. 113-
Cryptography
- B. J. Phillips, N. Burgess:
Implementing 1, 024-Bit RSA Exponentiation on a 32-Bit Processor Core. 127-137 - Zhijie Shi, Ruby B. Lee:
Bit Permutation Instructions for Accelerating Software Cryptography. 138-148 - William L. Freking, Keshab K. Parhi:
Performance-Scalable Array Architectures for Modular Multiplication. 149-
Digital Signal Processing
- Ahmed M. Shams, Magdy A. Bayoumi:
A 108 Gbps, 1.5 GHz 1D-DCT Architecture. 163-172 - Sridhar Rajagopal, Srikrishna Bhashyam, Joseph R. Cavallaro, Behnaam Aazhang:
Efficient VLSI Architectures for Baseband Signal Processing in Wireless Base-Station Receivers. 173-184 - Naraig Manjikian:
A Vector Multiprocessor for Real-Time Multi-User Detection in Spread-Spectrum Communication. 185-194 - V. S. Gierenz, Oliver Weiss, Tobias G. Noll, I. Carew, Jonathan J. Ashley, Razmik Karabed:
A 550 Mb/s Radix-4 Bit-level Pipelined 16-State 0.25-mu m CMOS Viterbi Decoder. 195-
Arithmetic
- Marc Daumas, David W. Matula:
A Booth Multiplier Accepting Both a Redundant or a Non-Redundant Input with No Additional Delay. 205-214 - Javier Hormigo, Julio Villalba, Michael J. Schulte:
A Hardware Algorithm for Variable-Precision Logarithm. 215-224 - Lijun Gao, Keshab K. Parhi:
Block-Update Parallel Processing QRD-RLS Algorithm for Throughput Improvement with Low Power Consumption. 225-234 - Ohsang Kwon, Earl E. Swartzlander Jr., Kevin J. Nowka:
A 16-Bit x 16-Bit MAC Design Using Fast 5: 2 Compressors. 235-
Multiprocessor Systems
- Martin C. Herbordt, Honghai Zhang, Calvin Lin, Hong Rao, Jade Cravy:
Control for High-Speed PE Arrays. 247-257 - Andrea Di Blas, Richard Hughey:
Explicit SIMD Programming for Asynchronous Applications. 258-267 - Scott Bowden, Doran Wilde, Sanjay V. Rajopadhye:
Quadratic Control Signals in Linear Systolic Arrays. 268-275 - Mukul Khandelia, Shuvra S. Bhattacharyya:
Contention-Conscious Transaction Ordering in Embedded Multiprocessors. 276-
Application-Specific Architectures
- María A. Trenas, Juan López, Manuel Sánchez, Emilio L. Zapata, Francisco Argüello:
Architecture for Wavelet Packet Transform with Best Tree Searching. 289-298 - Marcus Bednara, Oliver Beyer, Jürgen Teich, Rolf Wanka:
Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter. 299-308 - Hans-Martin Blüthgen, Tobias G. Noll:
A Programmable Processor for Approximate String Matching with High Throughput Rate. 309-
Design Methodology
- H. Safiri, Majid Ahmadi, Graham A. Jullien, William C. Miller:
A New Algorithm for the Elimination of Common Subexpressions in Hardware Implementation of Digital Filters by Using Genetic Programming. 319-328 - Ramaswamy Govindarajan, Erik R. Altman, Guang R. Gao:
A Theory for Software-Hardware Co-Scheduling for ASIPs and Embedded Processors. 329-338 - Michel Auguin, Luc Bianco, Laurent Capella, Emmanuel Gresset:
Partitioning Conditional Data Flow Graphs for Embedded System Design. 339-348 - Dirk Fimmel:
Generation of Scheduling Functions Supporting LSGP-Partitioning. 349-
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2026-05-18 23:24 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
