default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDASAP 1994: San Francisco, CA, USA
- International Conference on Application Specific Array Processors, ASAP 1994, Proceedings, San Francisco, CA, USA, 22-24 August, 1994. IEEE 1994, ISBN 0-8186-6517-3
- Jean Vuillemin:
Fast linear Hough transform. 1-9 - Mohan Vishwanath:
Algorithms and architectures for hierarchical compression of video. 10-21 - Richard L. Walke, Roger Evans, Roger F. Woods
, G. Floyd, K. W. Wood:
A high performance IIR filter chip and its evaluation system. 22-32 - John V. McCanny, Yi Hu, M. Yan:
Automated design of DSP array processor chips. 33-44 - Miodrag Potkonjak, Mani B. Srivastava:
Behavioral synthesis of high performance, low cost, and low power application specific processors for linear computations. 45-56 - Bongjin Jung, Yongjin Jeong, Wayne P. Burleson:
Distributed control synthesis for data-dependent iterative algorithms. 57-68 - Raminder Singh Bajwa, Chetana N. Keltcher, Paul Keltcher, Mary Jane Irwin:
Rapid prototyping with programmable control paths. 69-74 - Ramaswamy Govindarajan, Guang R. Gao, Palash Desai:
Minimizing memory requirements in rate-optimal schedules. 75-86 - Carol Hernandez, Daniel P. Siewiorek, Zary Segall:
A methodology for performance prediction of Sphinx I in multi-computer architectures. 87-98 - J. C. DeSouza-Batista, Alice C. Parker:
Optimal synthesis of application specific heterogeneous pipelined multiprocessors. 99-110 - W. H. Chou, Sun-Yuan Kung:
Register transfer modeling and simulation for array processors. 111-122 - Hyesook Lim, Earl E. Swartzlander Jr.:
A systolic array for 2-D DFT and 2-D DCT. 123-131 - Tonia G. Morris, Stephen P. DeWeerth:
Analog VLSI arrays for morphological image processing. 132-142 - Luca Breveglieri, Vincenzo Piuri:
A fast pipelined FFT unit. 143-151 - Lei Lin, Vijay K. Jain:
Parallel architectures for computing the Hough transform and CT image reconstruction. 152-163 - Catherine Dezan, Patrice Quinton:
Verification of regular architectures using ALPHA: a case study. 164-175 - Chris J. Scheiman, Peter R. Cappello:
A processor-time-minimal schedule for the standard tensor product algorithm. 176-187 - Luigi Dadda, Sami J. Inkinen, Vincenzo Piuri:
A processor for calorimetry at the Large Hadron Collider in the FERMI project. 188-199 - Doran K. Wilde, Oumarou Sie:
Regular array synthesis using ALPHA. 200-211 - Catherine Mongenet:
Data compiling for systems of affine recurrence equations. 212-223 - Philippe Clauss, Guy-René Perrin:
Optimal mapping of systolic algorithms by regular instruction shifts. 224-235 - Hyuk-Jae Lee, José A. B. Fortes:
On the injectivity of modular mappings. 236-247 - Michael J. Schulte, Earl E. Swartzlander Jr.:
A variable-precision interval arithmetic processor. 248-258 - Tracy C. Denk, Keshab K. Parhi:
Architectures for lattice structure based orthonormal discrete wavelet transforms. 259-270 - Johannes Kneip, Karsten Rönner, Peter Pirsch:
A data path array with shared memory as core of a high performance DSP. 271-282 - Jongwoo Bae, Viktor K. Prasanna, Heonchul Park:
Synthesis of a class of data format converters with specified delays. 283-294 - Tudor Jebelean:
Designing systolic arrays for integer GCD computation. 295-301 - Rumen Andonov, Sanjay V. Rajopadhye:
A sparse knapsack algo-tech-cuit and its synthesis. 302-313 - Ed F. Deprettere, Gerben J. Hekstra, Li-Sheng Shen, Jichun Bu, Gerrit Boersma:
A parallel system for photo realistic artificial scene rendering. 314-323 - Shen-Fu Hsiao, Jean-Marc Delosme:
Parallel processing of complex data using quaternion and pseudo-quaternion CORDIC algorithms. 324-335 - Manjit Borah, Raminder Singh Bajwa, Sridhar Hannenhalli, Mary Jane Irwin:
A SIMD solution to the sequence comparison problem on the MGAP. 336-345 - Céline Verdier, Emmanuel Boutillon, Anne Lafage, Alain Demeure:
Access and alignment of arrays for a bidimensional parallel memory. 346-356 - Venkatavasu Bokka, Himabindu Gurla, Stephan Olariu, James L. Schwing:
Constant-time triangulation problems on reconfigurable meshes. 357-368 - Martin Neschen:
A scalable bit-sequential SIMD array for nearest-neighbor classification using the city-block metric. 369-380 - Markus Schwarz, Bedrich J. Hosticka, M. Kesper, Peter Richert, Michael Scholles:
A parallel DSP-based neural network emulator with CMOS VLSI packet switching hardware. 381-391 - Rong Lin, Stephan Olariu, James L. Schwing:
An efficient VLSI architecture for digital geometry. 392-403 - Reiner W. Hartenstein, Rainer Kress, Helmut Reinig:
A dynamically reconfigurable wavefront array architecture for evaluation of expressions. 404-414 - Jan Rosseel, Francky Catthoor, Hugo De Man:
An optimisation methodology for array mapping of affine recurrence equations in video and image processing. 415-426 - Francky Catthoor, Werner Geurts, Hugo De Man:
Loop transformation methodology for fixed-rate video, image and telecom processing applications. 427-438 - Weijia Shang, Zhongliang Shu:
Data alignment of loop nests without nonlocal communications. 439-450
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2026-05-20 23:13 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
