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ORCIDASAP 1990: Princeton, NJ, USA
- Application Specific Array Processors, ASAP 1990. Proceedings of the International Conference on, Princeton, NJ, USA, 5-7 Sept., 1990. IEEE 1990, ISBN 0-8186-9089-5
- Philippe Clauss, Catherine Mongenet, Guy-René Perrin:
Calculus of space-optimal mappings of systolic algorithms on processor arrays. 4-18 - Chris J. Scheiman, Peter R. Cappello:
A processor-time minimal systolic array for transitive closure. 19-30 - Jichun Bu, Ed F. Deprettere, Lothar Thiele:
Systolic array implementation of nested loop programs. 31-42 - Richard H. Bayford:
The bit-serial systolic back-projection engine (BSSBPE). 43-54 - Soon Myoung Chung:
A database machine based on surrogate files. 55-66 - John Nelson, Abdur Rahman, Eamonn McQuade:
Systolic architectures for decoding Reed-Solomon codes. 67-77 - Chen-Mie Wu, Robert Michael Owens, Mary Jane Irwin:
Mapping high-dimension wavefront computations to silicon. 78-89 - Jenq-Neng Hwang, Jing-Ming Jong:
Systolic architecture for 2-D rank order filtering. 90-99 - Christophe Mauras, Patrice Quinton, Sanjay V. Rajopadhye, Yannick Saouter
:
Scheduling affine parameterized recurrences by means of Variable Dependent Timing Functions. 100-110 - Maya B. Gokhale, Andrew Kopser, Sara P. Lucas, Ronald G. Minnich:
The Logic Description Generator. 111-120 - Chi-Min Liu, Chein-Wei Jen:
Recursive algorithms for AR spectral estimation and their array realizations. 121-132 - Wayne Luk:
Analysing parametrised designs by non-standard interpretation. 133-144 - Y. Hu, John V. McCanny, M. Yan:
Systolic VLSI compiler (SVC) for high performance vector quantisation chips. 145-155 - Jan Rosseel, Francky Catthoor, Hugo De Man:
Extensions to linear mapping for regular arrays with complex processing elements. 156-167 - Jens Franzen:
Design of run-time fault-tolerant arrays of self-checking processing elements. 168-179 - Junichiro Makino, Tomoyoshi Ito, Toshikazu Ebisuzaki, Daiichiro Sugimoto:
GRAPE: a special-purpose computer for N-body problems. 180-189 - Brent Baxter, George W. Cox, Thomas R. Gross, H. T. Kung, David R. O'Hallaron, Craig Peterson, Jon A. Webb, Paul Wiley:
Building blocks for a new generation of application specific computing systems. 190-201 - Dhabaleswar Kumar Panda, Kai Hwang:
Reconfigurable vector register windows for fast matrix computation on the orthogonal multiprocessor. 202-213 - Didier Lattard, Bernard Faure, Guy Mazaré:
Massively parallel architecture: application to neural net emulation and image reconstruction. 214-225 - Takao Nishitani, Ichiro Tamitani, Hidenobu Harasaki, Mitsuharu Yano:
A real-time software programmable processor for HDTV and stereo scope signals. 226-234 - Jouko O. Viitanen, Tapio Korpiharju, Jarmo Takala, Hannu Kiminkinen:
Mapping algorithms onto the TUT cellular array processor. 235-246 - Scott T. Toborg:
A 3-D wafer scale architecture for early vision processing. 247-258 - V. K. Prasanna Kumar, K. Wojtek Przytula:
Algorithmic mapping of neural network models onto parallel SIMD machines. 259-271 - Miguel Valero-García, Juan J. Navarro, José M. Llabería, Mateo Valero:
Implementation of systolic algorithms using pipelined functional units. 272-283 - Neil M. Wigley, Graham A. Jullien:
Array processing on finite polynomial rings. 284-295 - Nelson Morgan, James Beck, Phil Kohn, Jeffrey A. Bilmes, Eric Allman, Joachim Beer:
The RAP: a ring array processor for layered network calculations. 296-308 - Zarir B. Sarkari, Alexander Skavantzos:
Linear arrays for residue mappers. 309-316 - Josef G. Krammer, Hendrikus Arif:
A fault-tolerant two-dimensional sorting network. 317-328 - Phill K. Rhee, Jung H. Kim:
Channel complexity analysis for reconfigurable VLSI/WSI processor arrays. 329-340 - Keshab K. Parhi, Ching-Yi Wang:
Digit-serial DSP architectures. 341-351 - Keping Chen, Per-Erik Danielsson, Anders Åström:
PASIC. A sensor/processor array for computer vision. 352-366 - Jonathan Wayne Mills, Charles A. Daffinger:
An analog VLSI array processor for classical and connectionist AI. 367-378 - Rajinder Jit Singh, John V. McCanny:
Systolic two-port adaptor for high performance wave digital filtering. 379-388 - C. C. Chiang, H. C. Fu:
An improved multilayer neural model and array processor implementation. 389-400 - Anna Antola, Nello Scarabottolo:
Reconfiguration of FFT arrays: a flow-driven approach. 401-413 - A. P. Marriott, Andrew W. G. Duller, Richard H. Storer, Andrew R. Thomson, Mike R. Pout:
Towards the automated design of application specific array processors (ASAPs). 414-425 - Jack S. N. Jean:
Fault-tolerant array processors using N-and-half-track switches. 426-437 - E. Theodore L. Omtzigt:
Domain flow and streaming architectures. 438-447 - Rory Doyle, Patrick Fitzpatrick, John Nelson:
An improved systolic extended Euclidean algorithm for Reed-Solomon decoding: design and implementation. 448-456 - Stewart G. Smith, Julian G. Payne, Ralph W. Morgan:
Digit-serial VLSI microarchitecture. 457-468 - Jonathan Wayne Mills, Charles A. Daffinger:
CMOS VLSI Lukasiewicz logic arrays. 469-480 - G. Jack Lipovski:
Dynamic systolic associative memory chip. 481-492 - R. M. Lea:
ASP modules: building-blocks for application-specific massively parallel processors. 493-504 - Patrice Frison, Eric Gautrin, Dominique Lavenier, J. L. Scharbarg:
Designing specific systolic arrays with the API15C chip. 505-517 - Bruce R. Musicus, Amnon Aliphas, Alexander J. Wei:
A prototype for a fault tolerant parallel digital signal processor. 518-529 - Luigi Dadda:
Byte-serial convolvers. 530-541 - Irving S. Reed, Ming-Tang Shih, E. Hendon, Trieu-Kien Truong, Donald W. Tufts:
A VLSI architecture for simplified arithmetic Fourier transform algorithm. 542-553 - Ulrich Ramacher, Wolfgang Raab:
Fine-grain system architectures for systolic emulation of neural algorithms. 554-566 - Pascal Fernandez, Pascal Adam, Didier Juvin, Jean-Luc Basille:
Programming environment for a line processor-SYMPATI-2. 567-578 - Deepak Rana, Charles C. Weems:
A feedback concentrator for the Image Understanding Architecture. 579-590 - Jichun Bu, Ed F. Deprettere, Patrick M. Dewilde:
A design methodology for fixed-size systolic arrays. 591-602 - Khaled M. Elleithy, Magdy A. Bayoumi:
A formal design methodology for parallel architectures. 603-614 - David B. Shu, J. Gregory Nash, Charles C. Weems:
A multiple-level heterogeneous architecture for image understanding. 615-627 - Dhiraj K. Pradhan:
Application specific VLSI architectures based on De Bruijn graphs. 628-640 - Jaime H. Moreno, Tomás Lang:
A graph-based approach to map matrix algorithms onto local-access processor arrays. 641-652 - Yaohan Chu:
Application-specific coprocessor computer architecture. 653-664 - Zicheng Guo, Rami G. Melhem:
Embedding pyramids in array processors with pipelined busses. 665-676 - Atsunobu Hiraiwa, Masahiro Fujita, Shigeru Kurosu, Shigeru Arisawa, Makoto Inoue:
Implementation of ANN on RISC processor array. 677-688 - Simon Haykin, Peter Weber, Bob Cho, Terry Greenlay, Jim Orlando, Cong Deng, Richard Mann:
Systolic-based computing machinery for radar signal processing studies. 689-699 - John G. McWhirter, David S. Broomhead, T. J. Shepherd:
A systolic array for nonlinear adaptive filtering and pattern recognition. 700-711 - C. S. Jeong, M. H. Kim:
Parallel algorithm for traveling salesman problem on SIMD machines using simulated annealing. 712-721 - C. Thomas Gray, Wentai Liu, Thomas A. Hughes, Ralph K. Cavin III:
The design of a high-performance scalable architecture for image processing applications. 722-733 - William P. Marnane, Will R. Moore:
Testing a motion estimator array. 734-745 - Abdelhamid Benaini, Yves Robert:
Spacetime-minimal systolic architectures for Gaussian elimination and the algebraic path problem. 746-757 - K. J. Ray Liu, Shih-Fu Hsieh, Kung Yao:
Two-level pipelined implementation of systolic block Householder transformation with application to RLS algorithm. 758-769 - Jean-Marc Delosme:
Bit-level systolic algorithm for the symmetric eigenvalue problem. 770-781 - Richard K. Squier, Kenneth Steiglitz:
A practical runtime test method for parallel lattice-gas automata. 782-793 - P. S. Tseng:
A systolic array programming language. 794-803
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