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ORCID32nd ARITH 2025: El Paso, TX, USA
- IEEE 32nd Symposium on Computer Arithmetic, ARITH 2025, El Paso, TX, USA, May 4-7, 2025. IEEE 2025, ISBN 979-8-3315-2159-2
- Bhargav Kulkarni, Pavel Panchekha:
Mixing Condition Numbers and Oracles for Accurate Floating-point Debugging. 101-108 - Saeid Gorgin, Amirhossein Sadr, Dara Rahmati, Jungrae Kim:
A Generic Modulo-(2n±δ) Addition Algorithm via Two-Valued Digit Encoding. 85-92 - Andrew W. Fitzgibbon, Stephen Felix:
On Stochastic Rounding with Few Random Bits. 133-140 - Albin Ahlback, Fredrik Johansson:
Fast Basecases for Arbitrary-Size Multiplication. 53-60 - Romain Bouarah, Florent de Dinechin:
Hardware Fixed-Point 2D and 3D norms. 29-36 - Laslo Hunhold, James Quinlan:
Evaluation of Bfloat16, Posit, and Takum Arithmetics in Sparse Linear Solvers. 61-68 - Christoph M. Wintersteiger:
Formal Verification of the IEEE P3109 Standard for Binary Floating-Point Formats for Machine Learning. 157-160 - Ping Tak Peter Tang:
Rounding Error Statistics as Numerics Signature. 93-100 - Sélène Corbineau, Paul Zimmermann:
Correct Rounding in Double Extended Precision. 117-124 - Orégane Desrentes, Benoît Dupont de Dinechin, Florent de Dinechin:
Double-Word Decomposition in a Combined FP16, BF16 and FP32 Dot Product Add Operator. 73-80 - Claude-Pierre Jeannerod, Paul Zimmermann:
FastTwoSum revisited. 141-148 - Toru Koizumi, Ryota Shioya, Takuya Yamauchi, Tomoya Adachi, Ken Namura, Jun Makino:
Trailing-Ones Anticipation for Reducing the Latency of the Rounding Incrementer in FP FMA Units. 21-28 - Frédéric Pétrot:
Experimental Software and Hardware Evaluation of Ad-Hoc Constant Division Routines. 69-72 - Rémi Garcia, Léo Pradels, Silviu-Ioan Filip, Olivier Sentieys:
Hardware-Aware Training for Multiplierless Convolutional Neural Networks. 9-16 - Jackson Vanover, James Demmel, Xiaoye Sherry Li, Cindy Rubio-González:
Excvate: Spoofing Exceptions and Solving Constraints to Test Exception Handling in Numerical Libraries. 109-116 - Hanmei Yang, Summer Deng, Amit Nagpal, Maxim Naumov, Mohammad Janani, Tongping Liu, Hui Guan:
An Empirical Study of Microscaling Formats for Low-Precision LLM Training. 1-8 - Shing Wai Pun
, Bozhang Bao, Silviu-Ioan Filip, Guy Lemieux, John V. Kim, Nazar Misyats, Nirvik Pande, Victor Ravain, Robert Sherrick:
Range Extension with Supernormals for Mixed-Precision 8-bit DNN Training. 1-4 - Per Larsson-Edefors, Erik Börjeson:
Implementation Evaluation of Fixed-Point Multipliers for Complex Numbers. 81-84 - Sol Swords, Cuong Chau:
Robust, End-to-end Correctness Proofs of Industrial Divide and Square Root RTL Designs. 149-156 - Paul Caprioli:
On the Flop and Flap Counts of the 2, 8-Split-Radix FFT. 45-52 - Run Wang, Gamze Islamoglu, Andrea Belano, Viviane Potocnik, Francesco Conti, Angelo Garofalo, Luca Benini:
VEXP: A Low-Cost RISC-V ISA Extension for Accelerated Softmax Computation in Transformers. 37-44 - Thanh Son Nguyen, Alexey Solovyev, Mark G. Arnold, Ganesh Gopalakrishnan:
Rigorous Error Analysis for Logarithmic Number Systems. 125-132
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